About 10 years ago Cisco was the largest buyer of Flash memory. Is the recent demand for cloud storage, data centers, and servers a major source of demand for Flash and DRAM memories.
Ron Maltiel
Exclusive: Google, Amazon, and Microsoft Swarm China for Network Gear
http://www.wired.com/wiredenterprise/2012/03/google-microsoft-network-gear/
By Cade Metz Email Author March 30, 2012 | 6:36 am |
J.R. Rivers once built networking hardware at Google. Now he helps web
giants buy their networking hardware directly from China and Taiwan.
Photo: Jon Snyder/Wired
Google, Amazon, Microsoft, and Facebook buy more networking hardware
than practically anyone else on earth. After all, these are the giants
of the internet. But at the same time, they're buying less and less
gear from Cisco, HP, Juniper, and the rest of the world's largest
networking vendors. It's an irony that could lead to a major shift in
the worldwide hardware market.
Over the past few years, the giants of the web have changed the way
they purchase tens of thousands of the network switches inside the
massive data centers driving their online services, quietly moving
away from U.S.-based sellers to buy cheaper gear in bulk straight from
China and Taiwan. According to J.R. Rivers — an ex-Google engineer —
Google has built its own gear in tandem with varous Asian
manufacturers for several years, and according to James Liao — who
spent two years selling hardware for Taiwan-based manufacturer Quanta
— Facebook, Amazon, and Microsoft are purchasing at least some of
their networking switches from Asian firms as well.
"My biggest customers were these big data center [companies], so I
know all of them pretty well," Liao says. "They all have different
ways of solving their networking problems, but they have all moved
away from big networking companies like Cisco or Juniper or [the
Dell-owned] Force10."
The move away from U.S. network equipment stalwarts is one of the
best-kept secrets in Silicon Valley. Some web giants consider their
networking hardware strategy a competitive advantage that must be
hidden from rivals. Others just don't want to anger their business
partners in the hardware sector by talking about the shift. But cloud
computing is an arms race. The biggest web companies on earth are
competing to see who can deliver their services to the most people in
the shortest amount of time at the lowest cost. And the cheapest arms
come straight from Asia.
J.R. Rivers is one of the arms dealers. He runs a company called
Cumulus Networks that helps the giants of the web — and other outfits
— buy their networking hardware directly from "original design
manufacturers," or ODMs, in China and Taiwan. And he's worked in this
world for an awfully long time. He's one of the Google engineers who
secretly designed a new breed of networking switch for the company's
data centers, the massive computing facilities that drive its search
engine and the rest of its web services.
Rivers joined Google in October 2005, after five ears as a
distinguished engineer at Cisco, the company that dominated the
worldwide market for networking gear. At the time, Google was still
connecting its servers using standard networking switches from the
likes of Cisco and Force10 Networks. But these mass-market switches
just didn't suit Google's unusually large operation.
"When Google looked at their network, they need high-bandwidth
connections between their servers and they wanted to be able to manage
things — at scale," Rivers says. "With the traditional enterprise
networking vendors, they just couldn't get there. The cost was too
high, and the systems were too closed to be manageable on a network of
that size."
So Google drew up its own designs — working alongside manufacturers in
Taiwan and China — and cut the Ciscos and the Force10s out of the
equation. The Ciscos and the Force10s build their gear with many of
those same manufacturers. Google removed the middlemen.
The search giant does much the same with its servers, buying
custom-built machines straight from Asia rather than going through
traditional sellers such as Dell and HP. Because its web services were
used by such an enormous number of people, Google faced all sorts of
data center problems no one else faced — problems of power and space
as well as cost and logistics. So it built all sorts of custom
hardware to solve those problems.
"They all have different ways of solving their networking problems,
but they have all moved away from big networking companies like Cisco
or Juniper or Force10″
Now, the other giants of the web are running into the same issues, and
they too are going straight to Asia for hardware. Following closely
behind are companies that run large internal server farms, including
financial houses and healthcare outfits.
As J.R. Rivers serves this market with Cumulus Networks, James Liao is
doing much the same thing with a second startup called Pica8, offering
networking gear that comes straight from the ODMs. Pica8 is a spinoff
of Liao's former employer, Quanta — one of the companies that
manufactured Google's original networking switches, according to
Rivers.
According to Liao, tens of thousands of switches are already being
sold by the Asian ODMs directly to the likes of Amazon, Facebook, and
Microsoft. And that doesn't include the gear Google has bought over
the past seven years. "This is just the beginning," Liao says,
pointing out that these buyers operate the biggest data centers on
earth. These companies account for only a part of the
$7-billion-a-year Ethernet switch market, but as more and more outfits
move their operations into the proverbial cloud, the influence of
these web giants will only grow.
Liao estimates that Amazon, Microsoft, Facebook and others have bought
Asian network switches spanning "millions" of network ports — i.e.,
connections to servers — and he guesses that in 2011, about 60 percent
of these ports provided 10Gigabit Ethernet connections. According to
Matthias Machowinski — a directing analyst with Infonetics, a research
firm that tracks the networking market — the official market for
10Gigabit Ethernet spanned about 9 million ports in 2011.
J.R. Rivers declines to name the companies he's working with at
Cumulus Networks, but he confirms that some of the big-name web
outfits are already buying networking switches from ODMs in Asia. In
all likelihood, these companies are also purchasing switches from
other sources as well. Cisco says it has a "significant presence and
mindshare" in the big-name web market, and Juniper says it has a
relationship with all of the top five web players, pointing out that
data center networks require more gear than just switches. But the
market is on the move.
The Future of 'Web Giant 3.0′
"We are continuously exploring new infrastructure technologies that
may evolve further efficiencies across our portfolio. We normally have
discussions with ODMs and large and small OEMs to better understand
their capabilities and evaluate their products," reads a statement
sent to Wired by a Microsoft spokesperson and attributed to Dileep
Bhandarkar, a distinguished engineer who oversees the data centers
driving Microsoft's online services. But the statement did not
specifically address the purchase of networking gear.
Amazon did not respond to a request for comment about its hardware
practices, and a Google spokeswoman sent us a one-sentence statement:
"We work with a variety of vendors to manufacture the equipment we use
in our data centers," she said. These two companies — particularly
Google — are rather tightlipped about their data center practices.
"This supply chain change is nascent. But it's the most exciting thing
going on in Silicon Valley right now"
Facebook declined to discuss how it purchases networking gear, but in
response to secretive approach of Amazon and Google, the company has
openly discussed some of its other practices, and it has actually
shared its server and data center designs with the rest of the world.
It purchases its servers directly from Quanta and Wistron, another
Taiwanese ODM.
Martin Casado — the chief technology officier of a third Silicon
Valley networking startup, Nicira — confirms that the hardware market
is shifting to Asia. Offering a software platform that virtualizes
networking gear in much the same way that VMware virtualized servers,
Nicira helps some of the big web players build their networks. The
Nicira platform was designed specifically for companies along the
lines of Google that want to use cheap commodity switches to
physically construct their network but then do all the complex
management in software.
"If you're building web giant 3.0, you can go to Quanta in Taiwan and
buy crates … of switches," he says. "This supply chain change is
nascent. But it's the most exciting thing going on in Silicon Valley
right now."
Google Goes to Asia
According to J.R. Rivers, Google began work on its custom-built
networking switches in early 2005, before he arrived at the company.
In the beginning, River says, Google worked in tandem with Quanta and
other Asian ODMs. But eventually, he says, Google took all the
engineering work in house. Basically, he says, the company wasn't
happy with the work the ODMs did at the time. Google engineers would
design the switches, and then they would bring the completed designs
to contract manufacturers in Asia, outfits along the lines of Foxconn,
the Asian company that builds Apple's iPhones and iPads.
Google has never discussed its practices publicly, but rumors have
long indicated that the company built its networking switches in this
way. In 2007, research analyst Andrew Schmitt noticed that certain
manufacturers were producing enormous numbers of chips for 10Gigabit
Ethernet switches but that the switches themselves weren't actually
turning up on the market. "It didn't make sense to me why someone
would be building so much of a given component if there were no
customers that could use it," he says. "What I was able to determine
is that Google was purchasing switch chips straight from the comment
suppler."
"It didn't make sense to me why someone would be building so much of a
given component if there were no customers that could use it"
The switches Google was building typically sat at the top of a rack of
servers in the data center, connecting the servers to the rest of the
network. As Juniper points out, this is only part of the networking
hardware used in the data, but it's a large part.
Google, Rivers says, is a unique company. It has the wherewithal and
the talent to built its own switches, but other companies may not be
up to the task. With Cumulus Networks, J.R. Rivers and his partner,
Nolan Leake, are trying to grease the wheels. "[The other web players]
are trying to figure out what the best model is, and that's one of the
reasons we started up," Rivers says. "Google is unique in its
willingness to build something just because they know it can be done.
Most other people see a risk/reward trade-off. We seek to minimize
that risk."
Though Rivers declined to name the ODMs his company is working with,
he says that these are well-known manufacturers in Taiwan and China.
"We've been working for the last year on opening up a supply chain for
traditional ODMs who want to sell the hardware on the open market for
whoever wants to buy," he says. "For the buyers, there can be some
very meaningful cost savings. Companies like Cisco and Force10 are
just buying from these same ODMs and marking things up. Now, you can
go directly to the people who manufacture it."
This has become possible in recent years, Rivers says, because the
ODMs have slowly acquired more and more engineering talent. You can
now buy commodity gear from more places. "Networking is opening up
much like the transition from mainframes to RISC machines and later to
x86 servers," says Rivers' partner, Nolan Leake. "We're moving towards
a world where customers have more control over their destiny."
'The Arms Dealer'
Before spinning Pica8 out of Quanta, James Liao was already selling
similar networking switches to the big web players. Nicira's Martin
Casado refers to James Liao as "the arms dealer" in this networking
revolution. "He's the conduit between the rest of the world and
Quanta. He knows this space better than anyone," Casado says. "And I
love him because he talks like he's part of organized crime."
From July 2009 to September 2011, Liao was the senior director at
Quanta in charge of product strategy for network switching and data
center products. He was based in Silicon Valley, and his job was to
serve the giants of the web. He declines to go into much detail about
how these companies acquire their hardware, but he's unequivocal in
saying that the other big companies — Amazon, Microsoft, and Facebook
— are now following Google's lead in going directly to Asia for their
gear.
James Liao. Photo: Courtesy Liao
Networking switches, he says, have become a commodity. "They all use
the same chips. They have to same latency. They have the same
bandwidth. This is a clear signal that the hardware platform is
commoditizing," he says. "You can actually find a lot of [ODM]
suppliers that have the capability to manufacturer and design this
kind of platform."
Like Cumulus Network, Liao's new venture, Pica8, brings this low-cost
networking hardware to a much larger market. In the past, one of the
problems with buying directly from the ODMs is that you had build your
own software to drive your switches. But Pica8 aims to provide
software for those companies that don't want to build their own. The
company has open sourced an early version of this software — known as
Picos — and it plans to open source a more extensive version of the
platform next month.
"We give you the hardware and the software," Liao says. "If you take
our platform and compare it to Cisco, the protocol features we provide
and the hardware performance are all in the same range. The only
difference is that the price is 40 percent to 60 percent lower."
Though Pica8 spun off of Quanta, Liao says that the company will also
sell switches from other ODMs. But he declined to name them. But he
does say Pica8 is selling gear to Japanese telecom giant NTT and
Baidu, the company that dominates the Chinese search engine market.
Matthias Machowinski, of research firm Infonetics, says he is "very
much aware" of this trend, though he adds that it is extremely hard to
track. He says that the big web giants account for only a part of the
overall switch market — "the number of customers that might choose to
go down this route are very limited. Today, you can count them on one
hand, and maybe over the next two years, two hands might be enough" —
but he also acknowledges that as businesses move their applications
onto services such as Amazon EC2 and Microsoft Azure — rather than
running stuff in their own data centers — these web giants will
account for an even larger part of the switch market.
Like Server, Like Switch
This shadow networking market is a repeat of what happened in the
server world. Years ago, Google started building its own servers in
tandem with the Asian ODMs, and other web giants followed. These
companies are looking to save cost, but they're also looking to reduce
their power consumption, customizing machines so they're far more
efficient than their mass-market brethren.
In 2009, Google revealed some server designs it produced several years
before. But, as with networking practices, the company says very
little about its server gear. Amazon operates in much the same way.
But Facebook had taken a different approach. Last year, after building
its own data centers and working with various manufacturers to build
its own servers, the social networking giant open sourced these
designs to the rest of the world, hoping that others across the
industry can help improve those designs, buy more hardware based on
the designs, and ultimately drive down the price of the hardware.
"It's kind like buying couches. If you buy one, you go to a retail
store. If you buy 10,000 couches, you go straight to the factory"
This Open Compute Project already has several other big-name backers,
including Texas-based cloud computing outfit Rackspace and Japan's
NTT. And it doesn't stop at data centers and servers. Last month,
Frank Frankovsky — the ex-Dell man who oversees hardware design at
Facebook — told us that the company is in the midst of building its
own storage hardware and that these designs will be open sourced in
early May.
In these cases, Facebook and Amazon and Google and others bypassed
"original equipment manufacturers," or OEMs, such as Dell and HP. The
servers sold by the likes of HP and Dell are actually manufactured by
those same ODMs in Taiwan and China.
James Liao, of Pica8 and formerly of Quanta, does not work with
servers. But he says that it's common knowledge that — like Google and
Facebook — Amazon purchases at least some of its servers from ODMs in
Asia. "For servers, Facebook and Amazon are taking almost exactly the
same approach," he says. "Amazon also has some very high power
designers, but they don't do the design themselves. They come up with
a certain architecture and they tell the ODMs: 'This is my vision.
These are the goals. And I want help designing the hardware.'"
Now, Liao says, this same sort of thing is happening with, well,
everything. "All of the data center hardware is bought this way," Liao
says. "You can refer to Facebook as an example, where one of the big
projects inside the Open Compute effort is storage. Even the storage
side is being commoditized. Servers, storage, and networking — all of
them are going to this way."
Nolan Leake and J.R. Rivers of Cumulus Networks. Photo: Jon Snyder/Wired
Howard Wu — the president of greater China for Joyent, an Amazon-like
cloud computing outfit based in San Francisco — agrees. "If you're a
small business and you're going to buy five servers, you're going to
Dell or HP, because of the support services. But if you're a data
center operator and you're going to buy 10,000 servers, you're going
straight [to the ODMs]," he says. "It's kind like buying couches. If
you buy one, you go to a retail store. If you buy 10,000 couches, you
go straight to the factory."
That said, Joyent is not yet buying its gear from the ODMs.
"We are definitely in talks, but it hasn't actually happened yet," he
says. "We have other contractual obligations right now." The market
has not completely shifted to Asia. It's moving in stages. These web
companies have many suppliers — that's just good for businesses — and
in some cases, they're still buying hardware from the traditional
players — perhaps because they still have contracts in place.
Facebook, for instance, is still buying some servers from Dell and HP.
And Amazon is still buying custom servers from Rackable, a stateside
manufacturer, and apparently other outfits based here in America.
The hardware supply chain is vast and varied. But it's consolidating.
Now that they have the engineering talent, J.R. Rivers says, the ODMs
are transforming into OEMs. "The market is maturing to the point where
anyone can buy directly from ODMs," he says. "You don't have to be
Google."
Saturday, March 31, 2012
Wednesday, March 28, 2012
Micron/ Intel 20-nm 64G MLC NAND Flash Memory Reverse Engineered
Intel and Micron’s joint venture for process development, IM Flash Technologies (IMFT), has successfully developed and manufactured high density multi-level NAND flash memories with a 20-nm design rule for the first time. IMFT also revealed a fully planar floating gate cell design.
IMFT has introduced a cell planarization integrating with high-k/metal gate (HKMG) stack.For a new cell structure, oxide-nitride-oxide (ONO) inter-gate dielectric layer is replaced by a stack of high-k dielectrics to restore the FG to CG coupling ratio. Thinner polysilicon floating gate technology is likely adopted to lower the cell-to-cell interference.
An air gap isolation process is adopted to reduce capacitance coupling between cells (more below).
Ron Maltiel
Delving deep into Micron and Intel’s 20-nm 64-Gbit MLC NAND flash memory
http://www.eetimes.com/electronics-blogs/other/4369862/Delving-deep-into-Micron-and-Intel-s-20-nm-64-Gbit-MLC-NAND-flash-memory?pageNumber=0
Young-Min Kwon, 3/26/2012 7:38 PM EDT
UBM TechInsights recently analyzed IMFT's 20-nm, 64-Gbit MLC NAND to get a better understanding of the advanced process technologies and innovative cell architecture. The success of NAND flash memory in the semiconductor market is mainly driven by continuous and tremendous growth in the mobile phone and tablet PC markets, and the growth of adoption of high performance solid state drives (SSDs) as a replacement for hard drives in computers. As Intel and Micron jointly announced last year, a NAND flash product with a terabit capacity, comprising a simple stack of several dice, can be realized with the advent of 20-nm manufacturing technology in conjunction with a break-through concept in cell architecture.
During the past years, NAND flash has enjoyed the highest density among the commercial memories due to its excellent physical scalability and multi-level cell (MLC) approach with two or three bits per cell. However, the recent demand spike for NAND flash memories in portable electronics has resulted in a much drastic scaling down of the device structure of NAND to obtain higher density, faster speed and lower bit cost devices. The aggressive scaling of a cell size in NAND flash memory is expected to face severe barriers in sub-20-nm floating gate-based flash cell with conventional architecture.
In response to the challenges mentioned, Intel and Micron’s joint venture for process development, IM Flash Technologies (IMFT), aggressively pursued a NAND cell shrink, and, as a result, has successfully developed and manufactured high density multi-level NAND flash memories with a 20-nm design rule for the first time. IMFT also revealed an innovative memory structure with the introduction of a fully planar floating gate cell design. IMFT, often considered a leader in the NAND flash manufacturing process, has introduced a cell planarization integrating with high-k/metal gate (HKMG) stack that would considerably overcome many of the physical and electrical scaling challenges brought on by moving to the 20-nm node or further beyond.
UBM TechInsights recently analyzed IMFT's 20-nm 64Gbit MLC NAND to get a better understanding of the advanced process technologies and innovative cell architecture.
By introducing the 20-nm process technology in the production of their 64-Gbit MLCNAND flash memory, IMFT establishes itself as the leader in new process node implementation. Measuring in with a die size of just 117 mm2, this NAND device features an area size that is approximately a 30 percent reduction over the IMFT’s existing 25-nm 64-Gbit NAND flash. IMFT’s 64-Gbit NAND flash is fabricated in a single poly, metal gate and triple metal levels and is distributed in a 48-pin lead-free TSOP package. The 64-Gbit of single flash memory die is divided into four banks with one-sided bond pad arrangement and memory area efficiency is 52% which is comparable to previous 25-nm 64-Gbit NAND device having the die size of 162 mm2.
In a conventional NAND floating gate cell, the control gate (CG) and inter-poly dielectric wrap around the floating gate (FG) and coupling factor greatly relies on the floating gate sidewalls as shown in the figure below.
Conventional floating gate NAND (IMFT’s 25 nm NAND flash)
Delving deeper
For the 20-nm and below technology node, the cell spacing is already too narrow to allow a control gate plug between the floating gates. As a result, the NAND flash memory will have to adopt a planar cell configuration by eliminating the control gate-floating gate wraparound.
Charge trapping-based flash (CTF) memory had been considered as an alternative, with CTF having a planar cell structure, but unfortunately we have yet to see a successful debut in NAND production quite yet. With all these factors at play, metal as control gate in combination with a stack of high-k inter-gate dielectrics (IGD) above thinner floating gate would be the potential solution to continue the scaling of NAND flash beyond the 20-nm node with existing floating gate-based NAND flash technology.
Planar floating gate NAND (IMFT’s 20-nm NAND flash)
Key technologies in the process and new flash cell structure
IMFT's 20-nm technology with a fully planar cell structure and key process advances have overcome several critical problems of conventional floating gate cell architectures in such a small flash device:
• Control gate (CG) poly-Si filling to narrower space between adjacent floating gates
• Cell-to-cell interference
• Scaling limitation of inter-poly dielectric (IPD) and smaller CG to FG coupling ratio.
In order to manufacture a 20-nm NAND cell, advanced cell pitch reduction techniques (such as double patterning technology) are used for critical lithographic steps. To pattern below the 20-nm design rule, quad patterning technology will also have to be implemented to overcome the limitation of 193 nm ArF immersion double patterning. This, however, could be still a ways away as the extreme ultraviolet lithography (EUV) tool required to address this patterning issue is still too expensive for flash memory production. For this NAND component, a single flash cell measures around 40-nm in both the wordline and the bitline direction yielding a physical cell area of 0.0017 µm2. That makes this cell most likely the smallest cell in NAND production. A planar floating gate structure has been implemented in this NAND device, in conjunction with thin polysilicon floating gate, a stack of high-k inter-gate dielectrics (IGD), and metal control gate.
For a new cell structure, oxide-nitride-oxide (ONO) inter-gate dielectric layer is replaced by a stack of high-k dielectrics to restore the FG to CG coupling ratio which should be reduced in planar cell structure. Thinner polysilicon floating gate technology is likely adopted to lower the cell-to-cell interference. A metal gate-based wordline is defined by etching the multiple gate stacks using the hard mask layer. As the cell pitch is aggressively scaled, the increased capacitance coupling between cells is a severe issue, since increased cell-to-cell interference leads to cell performance degradation and reliability problem. In order to overcome these problems, an air gap isolation process is adopted for both cell gates and metal 1 bitlines. An air gap structure has been reported to act as a low dielectric constant gap filling materials. The bitline contacts are formed as a staggered layout to obtain better lithographic margin, and a NAND string has 68 wordlines.
New cell architecture combined with key integration technologies observed from IMFT’s 20-nm MLC NAND flash is very promising to further extend the life span of conventional floating gate flash memory with more aggressive cell scaling. However, with a further reduced geometry of floating gate, the electrons captured will be drastically decreased, which could result in the need to manage less than 20 electrons in 1x-nm MLC NAND flash. That’s why novel device concepts or alternative memory solutions, such as those found in IMFT’s latest NAND flash device, reveal a preparedness to replace NAND flash memory in near future since scaling demand and reliability challenges will be much higher in dominant mobile applications. For example, the CTF seen in this NAND coupled with 3-D configuration could be seen as a viable near-term alternative to current planar NAND flash technology while a large variety of new memory concepts are emerging and competing for the replacement of NAND flash memory. Floating gate NAND flash will eventually arrive at its scaling limit but it’s not quite hitting the wall just yet. It will be very interesting to see what changes IMFT, and other flash manufacturers, incorporate to overcome these scaling limitations in the future.
IMFT has introduced a cell planarization integrating with high-k/metal gate (HKMG) stack.For a new cell structure, oxide-nitride-oxide (ONO) inter-gate dielectric layer is replaced by a stack of high-k dielectrics to restore the FG to CG coupling ratio. Thinner polysilicon floating gate technology is likely adopted to lower the cell-to-cell interference.
An air gap isolation process is adopted to reduce capacitance coupling between cells (more below).
Ron Maltiel
Delving deep into Micron and Intel’s 20-nm 64-Gbit MLC NAND flash memory
http://www.eetimes.com/electronics-blogs/other/4369862/Delving-deep-into-Micron-and-Intel-s-20-nm-64-Gbit-MLC-NAND-flash-memory?pageNumber=0
Young-Min Kwon, 3/26/2012 7:38 PM EDT
UBM TechInsights recently analyzed IMFT's 20-nm, 64-Gbit MLC NAND to get a better understanding of the advanced process technologies and innovative cell architecture. The success of NAND flash memory in the semiconductor market is mainly driven by continuous and tremendous growth in the mobile phone and tablet PC markets, and the growth of adoption of high performance solid state drives (SSDs) as a replacement for hard drives in computers. As Intel and Micron jointly announced last year, a NAND flash product with a terabit capacity, comprising a simple stack of several dice, can be realized with the advent of 20-nm manufacturing technology in conjunction with a break-through concept in cell architecture.
During the past years, NAND flash has enjoyed the highest density among the commercial memories due to its excellent physical scalability and multi-level cell (MLC) approach with two or three bits per cell. However, the recent demand spike for NAND flash memories in portable electronics has resulted in a much drastic scaling down of the device structure of NAND to obtain higher density, faster speed and lower bit cost devices. The aggressive scaling of a cell size in NAND flash memory is expected to face severe barriers in sub-20-nm floating gate-based flash cell with conventional architecture.
In response to the challenges mentioned, Intel and Micron’s joint venture for process development, IM Flash Technologies (IMFT), aggressively pursued a NAND cell shrink, and, as a result, has successfully developed and manufactured high density multi-level NAND flash memories with a 20-nm design rule for the first time. IMFT also revealed an innovative memory structure with the introduction of a fully planar floating gate cell design. IMFT, often considered a leader in the NAND flash manufacturing process, has introduced a cell planarization integrating with high-k/metal gate (HKMG) stack that would considerably overcome many of the physical and electrical scaling challenges brought on by moving to the 20-nm node or further beyond.
UBM TechInsights recently analyzed IMFT's 20-nm 64Gbit MLC NAND to get a better understanding of the advanced process technologies and innovative cell architecture.
By introducing the 20-nm process technology in the production of their 64-Gbit MLCNAND flash memory, IMFT establishes itself as the leader in new process node implementation. Measuring in with a die size of just 117 mm2, this NAND device features an area size that is approximately a 30 percent reduction over the IMFT’s existing 25-nm 64-Gbit NAND flash. IMFT’s 64-Gbit NAND flash is fabricated in a single poly, metal gate and triple metal levels and is distributed in a 48-pin lead-free TSOP package. The 64-Gbit of single flash memory die is divided into four banks with one-sided bond pad arrangement and memory area efficiency is 52% which is comparable to previous 25-nm 64-Gbit NAND device having the die size of 162 mm2.
In a conventional NAND floating gate cell, the control gate (CG) and inter-poly dielectric wrap around the floating gate (FG) and coupling factor greatly relies on the floating gate sidewalls as shown in the figure below.
Conventional floating gate NAND (IMFT’s 25 nm NAND flash)
Delving deeper
For the 20-nm and below technology node, the cell spacing is already too narrow to allow a control gate plug between the floating gates. As a result, the NAND flash memory will have to adopt a planar cell configuration by eliminating the control gate-floating gate wraparound.
Charge trapping-based flash (CTF) memory had been considered as an alternative, with CTF having a planar cell structure, but unfortunately we have yet to see a successful debut in NAND production quite yet. With all these factors at play, metal as control gate in combination with a stack of high-k inter-gate dielectrics (IGD) above thinner floating gate would be the potential solution to continue the scaling of NAND flash beyond the 20-nm node with existing floating gate-based NAND flash technology.
Planar floating gate NAND (IMFT’s 20-nm NAND flash)
Key technologies in the process and new flash cell structure
IMFT's 20-nm technology with a fully planar cell structure and key process advances have overcome several critical problems of conventional floating gate cell architectures in such a small flash device:
• Control gate (CG) poly-Si filling to narrower space between adjacent floating gates
• Cell-to-cell interference
• Scaling limitation of inter-poly dielectric (IPD) and smaller CG to FG coupling ratio.
In order to manufacture a 20-nm NAND cell, advanced cell pitch reduction techniques (such as double patterning technology) are used for critical lithographic steps. To pattern below the 20-nm design rule, quad patterning technology will also have to be implemented to overcome the limitation of 193 nm ArF immersion double patterning. This, however, could be still a ways away as the extreme ultraviolet lithography (EUV) tool required to address this patterning issue is still too expensive for flash memory production. For this NAND component, a single flash cell measures around 40-nm in both the wordline and the bitline direction yielding a physical cell area of 0.0017 µm2. That makes this cell most likely the smallest cell in NAND production. A planar floating gate structure has been implemented in this NAND device, in conjunction with thin polysilicon floating gate, a stack of high-k inter-gate dielectrics (IGD), and metal control gate.
For a new cell structure, oxide-nitride-oxide (ONO) inter-gate dielectric layer is replaced by a stack of high-k dielectrics to restore the FG to CG coupling ratio which should be reduced in planar cell structure. Thinner polysilicon floating gate technology is likely adopted to lower the cell-to-cell interference. A metal gate-based wordline is defined by etching the multiple gate stacks using the hard mask layer. As the cell pitch is aggressively scaled, the increased capacitance coupling between cells is a severe issue, since increased cell-to-cell interference leads to cell performance degradation and reliability problem. In order to overcome these problems, an air gap isolation process is adopted for both cell gates and metal 1 bitlines. An air gap structure has been reported to act as a low dielectric constant gap filling materials. The bitline contacts are formed as a staggered layout to obtain better lithographic margin, and a NAND string has 68 wordlines.
New cell architecture combined with key integration technologies observed from IMFT’s 20-nm MLC NAND flash is very promising to further extend the life span of conventional floating gate flash memory with more aggressive cell scaling. However, with a further reduced geometry of floating gate, the electrons captured will be drastically decreased, which could result in the need to manage less than 20 electrons in 1x-nm MLC NAND flash. That’s why novel device concepts or alternative memory solutions, such as those found in IMFT’s latest NAND flash device, reveal a preparedness to replace NAND flash memory in near future since scaling demand and reliability challenges will be much higher in dominant mobile applications. For example, the CTF seen in this NAND coupled with 3-D configuration could be seen as a viable near-term alternative to current planar NAND flash technology while a large variety of new memory concepts are emerging and competing for the replacement of NAND flash memory. Floating gate NAND flash will eventually arrive at its scaling limit but it’s not quite hitting the wall just yet. It will be very interesting to see what changes IMFT, and other flash manufacturers, incorporate to overcome these scaling limitations in the future.
Tuesday, March 27, 2012
Foundry Rankings (Including Samsungs' iPad, iPhone Breakdown)
Samsung's foundry breakdown shows how much of its business is tied to the iPad, iPhone, and iTouch products. For example, in 2011, Samsung's foundry produced $1.975 billion worth of chips. Apple products were $1.5 billion of the total chips manufactured.
Both Samsung and Apple need to diversify from each other. The high cost of new fabs, current commitments, and the length of time it takes to bring up a new fab is slowing this transition. Intel could potentially be another candidate as a foundry for Apple.
Ron Maltiel
Samsung, Win Semi Gain Ground in Foundry Rankings
http://semimd.com/blog/2012/01/12/samsung-win-semi-gain-ground-in-foundry-rankings/
By Mark LaPedus, SemiMD senior editor
The rapid shift towards smartphones, tablets and other products has caused a major change in the foundry business — and overall rankings. Amid the changes, Samsung Electronics Co. Ltd. — and little-known Win Semiconductors Corp. — gained ground in the rankings in the foundry business in 2011, according to IC Insights Inc.
Samsung jumped one place to 4th in the foundry rankings in 2011, according to the firm. After Samsung — which saw 64 percent growth in the foundry business last year — the second fastest growing vendor was Taiwan’s Win Semiconductors, a gallium arsenide (GaAs) foundry specialist that saw 36 percent growth last year.
TSMC remained the world’s largest foundry vendor in terms of sales in 2011, followed in order by UMC, GlobalFoundries, Samsung, SMIC, TowerJazz, Vanguard, Dongbu, IBM and Magnachip, according to the firm.
In total, the pure-play foundry business hit $27.7 billion in 2011, up 4 percent from 2010, according to IC Insights. The IDM foundry business was $4.9 billion in 2011, up from $4.1 billion in 2010, according to the firm.
In addition, Taiwan captured the distinction of being the country/region with the largest share of installed wafer capacity in 2011, according to IC Insights. As of mid-2011, Taiwan held 21 percent of global capacity, surpassing Japan (19.7 percent) and Korea (16.8 percent) to take over top spot for the first time. The Americas region with 14.7 percent share and China with 8.9 percent of capacity rounded out the top five, according to the firm.
C.J. Muse, an analyst with Barclays Capital, said foundry capital spending is expected to hit $18.374 billion in 2012, flat from last year.
The wild cards
There are two wild cards in the foundry business: Intel Corp. and Samsung. Intel has dabbled in the foundry business in recent times and is not a real contender — yet. “Overall, IC Insights believes that the leading-edge IC foundry business is going to be very competitive between the three major advanced technology suppliers — TSMC, GlobalFoundries, and Samsung,” according to IC Insights.
Not long ago, Samsung was a minor player in the segment. But thanks to its business with Apple Inc., Samsung’s foundry sales jumped by 64 percent in 2011, according to IC Insights. In total, Samsung had foundry sales of $1.975 billion in 2011. Of that, Samsung’s foundry business for Apple represented a total of $1.528 billion, according to IC Insights.
Samsung foundry fortunes tied to Apple
“Samsung was ranked as the fourth largest foundry in 2011 and could challenge for the number three spot over the next few years,” according to IC Insights. “It is estimated that Samsung’s dedicated IC foundry capacity reached 90K 300mm wafers per month at the end of 2011 (50K in South Korea and 40K in Austin, Texas).”
“Using an average revenue per wafer figure of $2,500, Samsung’s foundry capacity has the potential to produce annual sales of $2.7 billion,” according to the research firm.
There are also rumors that Samsung could build another logic fab in Texas as part of a move to keep the Apple foundry business. And for some time, Intel has been also looking at Apple as a foundry customer.
“We believe that Intel’s best chance to make material progress outside of the PC market is to become a foundry and manufacture for Apple. However, Samsung (is) doubling its foundry capacity this year. Thus, we think this opportunity for Intel looks less likely in the future unless Intel changes course,” said Auguste Gus Richard, an analyst with Piper Jaffray & Co.
IC Insights believes Apple must move to another foundry over time. At the same time, Samsung must also expand its customer base. “As Apple begins to engage other foundries (e.g., TSMC) to produce its custom processors, Samsung will need to make up for these lost sales by signing up additional large-scale customers,” according to IC Insights.
“While Apple and Samsung have exchanged lawsuits regarding system level products, Apple is still very reliant on Samsung for its advanced IC processor production (e.g., A4 and A5). It should be noted that TSMC was working at 100 percent utilization in mid‐2011 and essentially had no ability to allocate large amounts of leading-edge production capacity to Apple devices,” according to IC Insights.
“There is no doubt that Apple is looking to diversify away from being so reliant on its major system level competitor (Samsung) for the production of its advanced ICs. However, this transition may be destined to happen over a few years rather than a few quarters,” according to the firm.
Besides Samsung, others are also expanding their fab capacities. As reported, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) recently held a groundbreaking ceremony in Taichung’s Central Taiwan Science Park for Phase 3 of its Fab 15 GigaFab. Fab 15, Phase 3 will be TSMC’s second GigaFab equipped for 20nm process technology. The first 300mm GigaFab, Fab 12 module 5, is located in Hsinchu. Capacity for the Fab 15 Phase 3 is 40,000 300mm wafers per month. In the future, TSMC will make 450mm wafers as well as finFETs at 14nm in Fab 15.
Another vendor, GlobalFoundries Inc., is starting off with a bang in 2012: The company’s 300-mm fab in New York has moved into initial production. As part of its major announcement, GlobalFoundries as well as IBM on Monday (Jan. 9) announced an agreement to jointly manufacture advanced chips at both companies’ semiconductor fabs.
As in 2010, GlobalFoundries was third in the 2011 foundry rankings. Semiconductor Manufacturing International Corp. fell one place to 5th in the rankings. Recently, the Shanghai-based foundry vendor announced that David N. K. Wang resigned as chief executive. It also fell into the red in its most recent quarter.
Israel’s TowerJazz, a specialty foundry, was sixth in the foundry rankings. In June, TowerJazz completed its previously announced acquisition of Micron Technology’s fabrication facility in Nishiwaki City, Hyogo, Japan. The acquisition nearly doubles TowerJazz’s current internal manufacturing capacity, increasing production by 60,000 wafers per month. TowerJazz hopes to achieve its expressed $1 billion annual revenue run rate target by 2014.
Two other specialty foundries, Vanguard and Dongbu, were next in the rankings. IBM was ninth. “Since IBM’s commitment to the high‐volume foundry business is uncertain, IC Insights believes that this leaves only Samsung as the primary high volume leading-edge IDM IC foundry of the future,” according to the firm.
M&A activity
Besides capacity expansions, the other trend in the foundry business is clear: consolidation. In 2009, for example, GlobalFoundries’ parent company acquired Chartered Semiconductor, which was then merged into GlobalFoundries. Last year, Taiwan foundry vendor United Microelectronics Corp. (UMC) took a majority stake in Chinese foundry He Jian Technology Suzhou Co. Ltd.
Recently, two Chinese foundries, Shanghai Hua Hong NEC Electronics Co. Ltd. (HHNEC) and Grace Semiconductor Manufacturing Corp. (GSMC) merged. “The combined sales of these two foundries would have been $565 million in 2011, which would have been enough to move the new entity into sixth place behind TowerJazz in the 2011 ranking,’’ according to IC Insights.
The next victim in the shakeout could be LFoundry, a small analog and mixed-signal foundry specialist in Germany that is struggling. In 2008, Japan’s Renesas Technology Corp. sold its fab in Germany – Renesas Semiconductor Europe (Landshut) GmbH (RSEL) – to Silicon Foundry Holding (SFH).
Samsung gains ground on foundry rivals
Both Samsung and Apple need to diversify from each other. The high cost of new fabs, current commitments, and the length of time it takes to bring up a new fab is slowing this transition. Intel could potentially be another candidate as a foundry for Apple.
Ron Maltiel
Samsung, Win Semi Gain Ground in Foundry Rankings
http://semimd.com/blog/2012/01/12/samsung-win-semi-gain-ground-in-foundry-rankings/
By Mark LaPedus, SemiMD senior editor
The rapid shift towards smartphones, tablets and other products has caused a major change in the foundry business — and overall rankings. Amid the changes, Samsung Electronics Co. Ltd. — and little-known Win Semiconductors Corp. — gained ground in the rankings in the foundry business in 2011, according to IC Insights Inc.
Samsung jumped one place to 4th in the foundry rankings in 2011, according to the firm. After Samsung — which saw 64 percent growth in the foundry business last year — the second fastest growing vendor was Taiwan’s Win Semiconductors, a gallium arsenide (GaAs) foundry specialist that saw 36 percent growth last year.
TSMC remained the world’s largest foundry vendor in terms of sales in 2011, followed in order by UMC, GlobalFoundries, Samsung, SMIC, TowerJazz, Vanguard, Dongbu, IBM and Magnachip, according to the firm.
In total, the pure-play foundry business hit $27.7 billion in 2011, up 4 percent from 2010, according to IC Insights. The IDM foundry business was $4.9 billion in 2011, up from $4.1 billion in 2010, according to the firm.
In addition, Taiwan captured the distinction of being the country/region with the largest share of installed wafer capacity in 2011, according to IC Insights. As of mid-2011, Taiwan held 21 percent of global capacity, surpassing Japan (19.7 percent) and Korea (16.8 percent) to take over top spot for the first time. The Americas region with 14.7 percent share and China with 8.9 percent of capacity rounded out the top five, according to the firm.
C.J. Muse, an analyst with Barclays Capital, said foundry capital spending is expected to hit $18.374 billion in 2012, flat from last year.
The wild cards
There are two wild cards in the foundry business: Intel Corp. and Samsung. Intel has dabbled in the foundry business in recent times and is not a real contender — yet. “Overall, IC Insights believes that the leading-edge IC foundry business is going to be very competitive between the three major advanced technology suppliers — TSMC, GlobalFoundries, and Samsung,” according to IC Insights.
Not long ago, Samsung was a minor player in the segment. But thanks to its business with Apple Inc., Samsung’s foundry sales jumped by 64 percent in 2011, according to IC Insights. In total, Samsung had foundry sales of $1.975 billion in 2011. Of that, Samsung’s foundry business for Apple represented a total of $1.528 billion, according to IC Insights.
Samsung foundry fortunes tied to Apple
“Samsung was ranked as the fourth largest foundry in 2011 and could challenge for the number three spot over the next few years,” according to IC Insights. “It is estimated that Samsung’s dedicated IC foundry capacity reached 90K 300mm wafers per month at the end of 2011 (50K in South Korea and 40K in Austin, Texas).”
“Using an average revenue per wafer figure of $2,500, Samsung’s foundry capacity has the potential to produce annual sales of $2.7 billion,” according to the research firm.
There are also rumors that Samsung could build another logic fab in Texas as part of a move to keep the Apple foundry business. And for some time, Intel has been also looking at Apple as a foundry customer.
“We believe that Intel’s best chance to make material progress outside of the PC market is to become a foundry and manufacture for Apple. However, Samsung (is) doubling its foundry capacity this year. Thus, we think this opportunity for Intel looks less likely in the future unless Intel changes course,” said Auguste Gus Richard, an analyst with Piper Jaffray & Co.
IC Insights believes Apple must move to another foundry over time. At the same time, Samsung must also expand its customer base. “As Apple begins to engage other foundries (e.g., TSMC) to produce its custom processors, Samsung will need to make up for these lost sales by signing up additional large-scale customers,” according to IC Insights.
“While Apple and Samsung have exchanged lawsuits regarding system level products, Apple is still very reliant on Samsung for its advanced IC processor production (e.g., A4 and A5). It should be noted that TSMC was working at 100 percent utilization in mid‐2011 and essentially had no ability to allocate large amounts of leading-edge production capacity to Apple devices,” according to IC Insights.
“There is no doubt that Apple is looking to diversify away from being so reliant on its major system level competitor (Samsung) for the production of its advanced ICs. However, this transition may be destined to happen over a few years rather than a few quarters,” according to the firm.
Besides Samsung, others are also expanding their fab capacities. As reported, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) recently held a groundbreaking ceremony in Taichung’s Central Taiwan Science Park for Phase 3 of its Fab 15 GigaFab. Fab 15, Phase 3 will be TSMC’s second GigaFab equipped for 20nm process technology. The first 300mm GigaFab, Fab 12 module 5, is located in Hsinchu. Capacity for the Fab 15 Phase 3 is 40,000 300mm wafers per month. In the future, TSMC will make 450mm wafers as well as finFETs at 14nm in Fab 15.
Another vendor, GlobalFoundries Inc., is starting off with a bang in 2012: The company’s 300-mm fab in New York has moved into initial production. As part of its major announcement, GlobalFoundries as well as IBM on Monday (Jan. 9) announced an agreement to jointly manufacture advanced chips at both companies’ semiconductor fabs.
As in 2010, GlobalFoundries was third in the 2011 foundry rankings. Semiconductor Manufacturing International Corp. fell one place to 5th in the rankings. Recently, the Shanghai-based foundry vendor announced that David N. K. Wang resigned as chief executive. It also fell into the red in its most recent quarter.
Israel’s TowerJazz, a specialty foundry, was sixth in the foundry rankings. In June, TowerJazz completed its previously announced acquisition of Micron Technology’s fabrication facility in Nishiwaki City, Hyogo, Japan. The acquisition nearly doubles TowerJazz’s current internal manufacturing capacity, increasing production by 60,000 wafers per month. TowerJazz hopes to achieve its expressed $1 billion annual revenue run rate target by 2014.
Two other specialty foundries, Vanguard and Dongbu, were next in the rankings. IBM was ninth. “Since IBM’s commitment to the high‐volume foundry business is uncertain, IC Insights believes that this leaves only Samsung as the primary high volume leading-edge IDM IC foundry of the future,” according to the firm.
M&A activity
Besides capacity expansions, the other trend in the foundry business is clear: consolidation. In 2009, for example, GlobalFoundries’ parent company acquired Chartered Semiconductor, which was then merged into GlobalFoundries. Last year, Taiwan foundry vendor United Microelectronics Corp. (UMC) took a majority stake in Chinese foundry He Jian Technology Suzhou Co. Ltd.
Recently, two Chinese foundries, Shanghai Hua Hong NEC Electronics Co. Ltd. (HHNEC) and Grace Semiconductor Manufacturing Corp. (GSMC) merged. “The combined sales of these two foundries would have been $565 million in 2011, which would have been enough to move the new entity into sixth place behind TowerJazz in the 2011 ranking,’’ according to IC Insights.
The next victim in the shakeout could be LFoundry, a small analog and mixed-signal foundry specialist in Germany that is struggling. In 2008, Japan’s Renesas Technology Corp. sold its fab in Germany – Renesas Semiconductor Europe (Landshut) GmbH (RSEL) – to Silicon Foundry Holding (SFH).
While FinFET Charging Ahead, Other 20nm challenges
While the industry is following Intel's lead with FinFET transistors, there are several additional major problems in continuing semiconductors technology scaling. Some key problems are discussed below.
More on 22nm challenges.
Ron Maltiel
Top Five Design and Manufacturing Challenges at 20nm
http://semimd.com/blog/2012/03/21/top-five-design-and-manufacturing-challenges-at-20nm/
By Mark LaPedus
The hottest topic in the leading-edge silicon foundry world centers around the shift from planar transistors to finFET structures at the 14nm process node.
GlobalFoundries, Samsung, TSMC and UMC are racing each other to develop finFETs at the 14nm node. But the industry is getting ahead of itself, as experts warn there are still enormous IC design and manufacturing challenges at the 20nm process node. The foundries will continue to use planar transistor structures at 28nm and 20nm, with plans to move to finFETs at 14nm.
Some but not all foundries are still struggling to ramp up their processes based on high-k/metal-gate schemes at the 28nm node. While vendors are seeing various challenges at 28nm, the 20nm node is expected to be even more daunting. “It’s a brave new world at 20nm,” said Tom Beckley, senior vice president of research and development for custom IC and signoff for the Silicon Realization Group at Cadence Design Systems Inc.
At 20nm, there are also economic factors involved, namely fab, process and design costs. And there are also technology challenges, such as the advent of double patterning, severe layout-dependent effects, as well as the introduction of a new and third layer of local interconnect in the design.
That layer — or the so-called middle of the line (MOL) — will likely become “disruptive” in the IC flow, said Luigi Capodieci, director of DFM/CAD and R&D Fellow at silicon foundry vendor GlobalFoundries Inc. Capodieci and Beckley were among the keynoters at the 13th International Symposium on Quality Electronic Design (ISQED) in Santa Clara, Calif. on Tuesday (March 20).
There are a multitude of design and manufacturing challenges at the 20nm node. Based on the keynote presentations from the two design/foundry experts at ISQED, here are five of the bigger design/manufacturing challenges — and trends — at 20nm:
1. The economics factors favor a select few
Chip scaling enables smaller devices at lower costs, but there are also some major ramifications: Fewer and fewer vendors can participate as the industry marches down to the smaller nodes. Only the players with deep pockets can afford to play at 20nm. It’s simply becoming too expensive for most to play at the bleeding-edge of IC design and manufacturing.
The foundries are seeing a clear trend at the leading-edge. “The number of tape outs is decreasing, but the volumes are much higher,” said GlobalFoundries’ Capodieci during his keynote at ISQED.
Citing International Business Strategies Inc. (IBS), a research firm, Cadence’s Beckley said at the 32/28nm nodes, a fab runs $3 billion, process R&D is $1.2 billion, IC design costs ranges from $50 million to $90 million, and mask costs are from $2 million to $3 million.
Citing the same research firm, he said at the 22/20nm nodes, a fab will cost $4 billion to $7 billion, process R&D runs from $2.1 billion to $3 billion, design costs run from between $120 million to $500 million, and mask costs are from $5 million to $8 million.
From his own data, he said EDA tool costs in total run from $800 million to $1.2 billion for the 22/20nm nodes, compared to $400 million to $500 million for 32nm/28nm. Another troubling trend is verification. “Verification times are exploding,” he added.
The solution to the problem? In the past, circuit designers and layout engineers lived in separate silos. The two groups will need to collaborate in order to deal with the complexities involved at 20nm and beyond, Beckley said.
2. Double patterning has (unfortunately) entered the spotlight
The IC industry has pushed 193nm wavelength lithography much further than previously thought. Amazingly, on the logic front, the IC industry is using today’s 193nm immersion scanners based on signal-exposure techniques at the 32nm/28nm nodes.
But due to the delays with the various next-generation lithography (NGL) candidates — namely extreme ultraviolet (EUV) — the industry must embrace 193nm lithography and multi-patterning at 20nm and perhaps beyond. Today, Toshiba Corp. and SanDisk Corp. are making 19nm NAND devices using 193nm immersion scanners — and with the help of a resolution enhancement technique (RET) called self-aligned double patterning. Meanwhile, at 22nm, Intel Corp. is using 193nm immersion — with the help of some form of double-patterning technique.
Double pattering involves separate exposures of the same layer using two photomasks, which, in turn, adds complexity and cost in chip manufacturing.
“At 20nm, the foundries will require double-patterning,” said Beckley during his ISQED keynote, but that “brings coloring” into the mix. In double-patterning, the layout patterns are split and decomposed into two masks. The polygons or features are assigned opposite colors.
The question is whether the coloring is managed by the designer or foundry. That process should not be managed by the foundry, he said. “Coloring must be managed within the design methodology and saved as an integral part of the IP,” he said.
At 20nm, the foundries will likely embrace a double-pattering technique that involves “litho-etch-litho-etch (LELE),” said GlobalFoundries’ Capodieci. LELE poses some challenges in terms of the composition/decomposition steps and overlay. “Overlay can cause local line width variations or local space CD variations depending on the process scheme, which translates into electrical degradation,” he said.
At 20nm, GlobalFoundries and its EDA partners are working on adding “double-patterning-aware” technologies to solve many of the issues. To get around many of these issues, the IC industry is banking on extreme ultraviolet (EUV) lithography. But EUV is late and is a question mark for 14nm. The problem continues to be the power source and throughput.
EUV remains the lithography technology for “tomorrow,” said Capodieci. “Tomorrow’s lithography is still happening tomorrow.”
3. New routing layers
At 28nm and above, the manufacturing flow consists of two parts: front-end-of-the-line (FEOL) and backend-of –the-line (BEOL). The FEOL involves the formation of the transistors and logic, while BEOL handles the vias, interconnects and other structures.
At 20nm, the foundries are now talking about a third layer of interconnect. That layer — or MOL — will become another challenge in the manufacturing flow, Capodieci said.
As a result, the industry will require “new methodologies” to address the new routing layer, said Cadence’s Beckley.
4. Severe layout-dependent effects
Beckley said severe layout-dependent effects are expected at all advanced nodes. Shallow trench isolation (STI) and well proximity effect (WPE) are two types of layout-dependent effects. So it is important that vendors get involved “early in the design stage to handle the parasitics,” he said.
5. More DFM to the rescue
Is Moore’s Law slowing down? “The answer is that it is not for the memory and processor IDMs, but definitely for the foundries,” said G. Dan Hutcheson, president of VLSI Research Inc. “The alarming thing about it is that the ability of foundries to convert their process development and tool investments into revenues has been steadily declining since 130nm. The importance of 130nm is that’s when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then.”
Is foundry model falling apart? (Source: VLSI)
”What’s more scary about the chart is that the decline is predictable, forming a steady downward trend,” said Hutcheson. ”Meanwhile, the fabless companies at the leading edge, such as Nvidia and Qualcomm are visibly concerned about their foundries’ ability to keep up with Moore’s Law. To stay in the game they need a steady decline in cost-per-transistor. If anything, this chart certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”
The solution? EDA houses, foundries and fabless chip makers must ”partner more closely,” he said. ”But this comes at a time when the foundries have become more mistrustful, communicating less about upcoming processes. One thing is clear: If these issues don’t get resolved, there will be a major restructuring of the industry.”
Amid these alarming trends, there is also pressure among chip makers to develop more robust designs — and ensure they can be manufactured in a timely fashion. To meet these challenges, IC vendors have recently embraced — and put more emphasis — on DFM. As part of the DFM equation, chips yields — and the yield enhancement process — have become even more critical.
Within that technology, GlobalFoundries has worked with Mentor to develop a flow to boost yields. In another major step to solve the problem, Cadence and GlobalFoundries recently teamed up to reduce the turnaround times for DFM signoff at 28nm. It’s likely that this technology will be migrated to 20nm.
Using Cadence’s “in-design” DFM tools, GlobalFoundries calls the technology DRC+. The core of the DRC+ flow is two-dimensional shape-based pattern matching, which offers speed improvements in error detection and fixing. This technology enables customers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.
In the DFM world, this is a step in the right direction. GlobalFoundries’ Capodieci said the technology is 10,000 times faster than simulations
More on 22nm challenges.
Ron Maltiel
Top Five Design and Manufacturing Challenges at 20nm
http://semimd.com/blog/2012/03/21/top-five-design-and-manufacturing-challenges-at-20nm/
By Mark LaPedus
The hottest topic in the leading-edge silicon foundry world centers around the shift from planar transistors to finFET structures at the 14nm process node.
GlobalFoundries, Samsung, TSMC and UMC are racing each other to develop finFETs at the 14nm node. But the industry is getting ahead of itself, as experts warn there are still enormous IC design and manufacturing challenges at the 20nm process node. The foundries will continue to use planar transistor structures at 28nm and 20nm, with plans to move to finFETs at 14nm.
Some but not all foundries are still struggling to ramp up their processes based on high-k/metal-gate schemes at the 28nm node. While vendors are seeing various challenges at 28nm, the 20nm node is expected to be even more daunting. “It’s a brave new world at 20nm,” said Tom Beckley, senior vice president of research and development for custom IC and signoff for the Silicon Realization Group at Cadence Design Systems Inc.
At 20nm, there are also economic factors involved, namely fab, process and design costs. And there are also technology challenges, such as the advent of double patterning, severe layout-dependent effects, as well as the introduction of a new and third layer of local interconnect in the design.
That layer — or the so-called middle of the line (MOL) — will likely become “disruptive” in the IC flow, said Luigi Capodieci, director of DFM/CAD and R&D Fellow at silicon foundry vendor GlobalFoundries Inc. Capodieci and Beckley were among the keynoters at the 13th International Symposium on Quality Electronic Design (ISQED) in Santa Clara, Calif. on Tuesday (March 20).
There are a multitude of design and manufacturing challenges at the 20nm node. Based on the keynote presentations from the two design/foundry experts at ISQED, here are five of the bigger design/manufacturing challenges — and trends — at 20nm:
1. The economics factors favor a select few
Chip scaling enables smaller devices at lower costs, but there are also some major ramifications: Fewer and fewer vendors can participate as the industry marches down to the smaller nodes. Only the players with deep pockets can afford to play at 20nm. It’s simply becoming too expensive for most to play at the bleeding-edge of IC design and manufacturing.
The foundries are seeing a clear trend at the leading-edge. “The number of tape outs is decreasing, but the volumes are much higher,” said GlobalFoundries’ Capodieci during his keynote at ISQED.
Citing International Business Strategies Inc. (IBS), a research firm, Cadence’s Beckley said at the 32/28nm nodes, a fab runs $3 billion, process R&D is $1.2 billion, IC design costs ranges from $50 million to $90 million, and mask costs are from $2 million to $3 million.
Citing the same research firm, he said at the 22/20nm nodes, a fab will cost $4 billion to $7 billion, process R&D runs from $2.1 billion to $3 billion, design costs run from between $120 million to $500 million, and mask costs are from $5 million to $8 million.
From his own data, he said EDA tool costs in total run from $800 million to $1.2 billion for the 22/20nm nodes, compared to $400 million to $500 million for 32nm/28nm. Another troubling trend is verification. “Verification times are exploding,” he added.
The solution to the problem? In the past, circuit designers and layout engineers lived in separate silos. The two groups will need to collaborate in order to deal with the complexities involved at 20nm and beyond, Beckley said.
2. Double patterning has (unfortunately) entered the spotlight
The IC industry has pushed 193nm wavelength lithography much further than previously thought. Amazingly, on the logic front, the IC industry is using today’s 193nm immersion scanners based on signal-exposure techniques at the 32nm/28nm nodes.
But due to the delays with the various next-generation lithography (NGL) candidates — namely extreme ultraviolet (EUV) — the industry must embrace 193nm lithography and multi-patterning at 20nm and perhaps beyond. Today, Toshiba Corp. and SanDisk Corp. are making 19nm NAND devices using 193nm immersion scanners — and with the help of a resolution enhancement technique (RET) called self-aligned double patterning. Meanwhile, at 22nm, Intel Corp. is using 193nm immersion — with the help of some form of double-patterning technique.
Double pattering involves separate exposures of the same layer using two photomasks, which, in turn, adds complexity and cost in chip manufacturing.
“At 20nm, the foundries will require double-patterning,” said Beckley during his ISQED keynote, but that “brings coloring” into the mix. In double-patterning, the layout patterns are split and decomposed into two masks. The polygons or features are assigned opposite colors.
The question is whether the coloring is managed by the designer or foundry. That process should not be managed by the foundry, he said. “Coloring must be managed within the design methodology and saved as an integral part of the IP,” he said.
At 20nm, the foundries will likely embrace a double-pattering technique that involves “litho-etch-litho-etch (LELE),” said GlobalFoundries’ Capodieci. LELE poses some challenges in terms of the composition/decomposition steps and overlay. “Overlay can cause local line width variations or local space CD variations depending on the process scheme, which translates into electrical degradation,” he said.
At 20nm, GlobalFoundries and its EDA partners are working on adding “double-patterning-aware” technologies to solve many of the issues. To get around many of these issues, the IC industry is banking on extreme ultraviolet (EUV) lithography. But EUV is late and is a question mark for 14nm. The problem continues to be the power source and throughput.
EUV remains the lithography technology for “tomorrow,” said Capodieci. “Tomorrow’s lithography is still happening tomorrow.”
3. New routing layers
At 28nm and above, the manufacturing flow consists of two parts: front-end-of-the-line (FEOL) and backend-of –the-line (BEOL). The FEOL involves the formation of the transistors and logic, while BEOL handles the vias, interconnects and other structures.
At 20nm, the foundries are now talking about a third layer of interconnect. That layer — or MOL — will become another challenge in the manufacturing flow, Capodieci said.
As a result, the industry will require “new methodologies” to address the new routing layer, said Cadence’s Beckley.
4. Severe layout-dependent effects
Beckley said severe layout-dependent effects are expected at all advanced nodes. Shallow trench isolation (STI) and well proximity effect (WPE) are two types of layout-dependent effects. So it is important that vendors get involved “early in the design stage to handle the parasitics,” he said.
5. More DFM to the rescue
Is Moore’s Law slowing down? “The answer is that it is not for the memory and processor IDMs, but definitely for the foundries,” said G. Dan Hutcheson, president of VLSI Research Inc. “The alarming thing about it is that the ability of foundries to convert their process development and tool investments into revenues has been steadily declining since 130nm. The importance of 130nm is that’s when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then.”
Is foundry model falling apart? (Source: VLSI)
”What’s more scary about the chart is that the decline is predictable, forming a steady downward trend,” said Hutcheson. ”Meanwhile, the fabless companies at the leading edge, such as Nvidia and Qualcomm are visibly concerned about their foundries’ ability to keep up with Moore’s Law. To stay in the game they need a steady decline in cost-per-transistor. If anything, this chart certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”
The solution? EDA houses, foundries and fabless chip makers must ”partner more closely,” he said. ”But this comes at a time when the foundries have become more mistrustful, communicating less about upcoming processes. One thing is clear: If these issues don’t get resolved, there will be a major restructuring of the industry.”
Amid these alarming trends, there is also pressure among chip makers to develop more robust designs — and ensure they can be manufactured in a timely fashion. To meet these challenges, IC vendors have recently embraced — and put more emphasis — on DFM. As part of the DFM equation, chips yields — and the yield enhancement process — have become even more critical.
Within that technology, GlobalFoundries has worked with Mentor to develop a flow to boost yields. In another major step to solve the problem, Cadence and GlobalFoundries recently teamed up to reduce the turnaround times for DFM signoff at 28nm. It’s likely that this technology will be migrated to 20nm.
Using Cadence’s “in-design” DFM tools, GlobalFoundries calls the technology DRC+. The core of the DRC+ flow is two-dimensional shape-based pattern matching, which offers speed improvements in error detection and fixing. This technology enables customers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.
In the DFM world, this is a step in the right direction. GlobalFoundries’ Capodieci said the technology is 10,000 times faster than simulations
Monday, March 26, 2012
Qualcomm, Intel Fastest Growing Semiconductor Companies
It is not surprising that Qualcomm, which supplies chips to the mobile revolution, grew 41.6% in 2011. However, Intel, which supply chips to the slow-growing PC market, increased its revenues by 20%. Acquisitions were key drivers for Intel's and Qualcomm's growth in 2011.
As I have been pointing out for many years the rankings are missing two major companies: Sandisk and ARM Holdings.
Ron Maltiel
Chip rankings: Intel had highest share in over 10 years
http://www.eetimes.com/electronics-news/4369843/Chip-rankings--Intel-had-highest-share-in-over-10-years
Dylan McGrath , 3/26/2012 4:34 PM EDT
Intel accounted for 15.6 percent of the overall semiconductor market in 2011, as brisk sales of its core chips and the acquisition of Infineon AG's wireless chip business unit helped the No. 1 chip vendor achieve its highest share of the overall chip market in more than 10 years, according to market research firm IHS iSuppli. SAN FRANCISCO—Intel Corp. accounted for 15.6 percent of the overall semiconductor market in 2011, as brisk sales of its core chips and the acquisition of Infineon AG's wireless chip business unit helped the No. 1 chip vendor achieve its highest share of the overall chip market in more than 10 years, according to market research firm IHS iSuppli.
Intel's overall market share in 2011 improved by 2.5 percentage points from 13.1 percent in 2010, according to IHS's final tally of the 2011 chip market. The firm issued a preliminary report on the 2011 chip vendors rankings last December.
"Intel in 2011 captured the headlines with its major surge in growth," said Dale Ford, head of electronics and semiconductor research for IHS, in a statement. "The company’s rise was spurred by soaring demand for its PC-oriented microprocessors, and for its NAND flash memory used in consumer and wireless products."
Intel's sales grew by 20.6 percent in 2011, the highest level of growth among the top 20 semiconductor vendors with the exceptions of Qualcomm Inc. and On Semiconductor Corp., each of which saw high levels of growth based on a combination of organic expansion and key acquisitions, IHS said.
In recent years, South Korea's Samsung Electronics Co. Ltd. had been getting closer to overtaking Intel and becoming the No. 1 chip supplier. But in 2011, Intel lengthened its lead over Samsung, which accounted for 9.2 percent of overall chip sales, unchanged from 2010, IHS said.
Based on the final numbers, IHS said the chip market grew by a paltry 1.3 percent in 2011, down from an earlier estimate by the firm of 1.9 percent growth. A sequential decline of 5.9 percent in the fourth quarter of 2011 pulled the full-year results down, IHS said.
Qualcomm grew 41.6 percent in 2011 to became the sixth largest chip vendor by sales, up from ninth in 2010, IHS said. Qualcomm accounted for 3.3 percent of overall chip sales, just behind No. 5 player Renesas Electronics Corp., which had 3.4 percent, according to IHS.
On Semi moved to No. 18 in chip sales in 2011, up from No. 26 in 2010, the largest jump of any vendor in the top 25, IHS said. Light-emitting diode (LED) maker Nichia Corp ranked No. 23 in chip sales in 2011, thanks to 34 percent growth, IHS said.
In 2011, just over half of 302 chip suppliers tracked by IHS grew sales compared with 2010, IHS said.
Overall, companies headquartered in the Americas saw the greatest improvement to their semiconductor revenues among all regions, at 7.5 percent growth, IHS said. In comparison, revenue fell 7.2 percent as a whole for Japanese firms, which suffered from the impact of the 2011 earthquake, according to the firm.
As I have been pointing out for many years the rankings are missing two major companies: Sandisk and ARM Holdings.
Ron Maltiel
Chip rankings: Intel had highest share in over 10 years
http://www.eetimes.com/electronics-news/4369843/Chip-rankings--Intel-had-highest-share-in-over-10-years
Dylan McGrath , 3/26/2012 4:34 PM EDT
Intel accounted for 15.6 percent of the overall semiconductor market in 2011, as brisk sales of its core chips and the acquisition of Infineon AG's wireless chip business unit helped the No. 1 chip vendor achieve its highest share of the overall chip market in more than 10 years, according to market research firm IHS iSuppli. SAN FRANCISCO—Intel Corp. accounted for 15.6 percent of the overall semiconductor market in 2011, as brisk sales of its core chips and the acquisition of Infineon AG's wireless chip business unit helped the No. 1 chip vendor achieve its highest share of the overall chip market in more than 10 years, according to market research firm IHS iSuppli.
Intel's overall market share in 2011 improved by 2.5 percentage points from 13.1 percent in 2010, according to IHS's final tally of the 2011 chip market. The firm issued a preliminary report on the 2011 chip vendors rankings last December.
"Intel in 2011 captured the headlines with its major surge in growth," said Dale Ford, head of electronics and semiconductor research for IHS, in a statement. "The company’s rise was spurred by soaring demand for its PC-oriented microprocessors, and for its NAND flash memory used in consumer and wireless products."
Intel's sales grew by 20.6 percent in 2011, the highest level of growth among the top 20 semiconductor vendors with the exceptions of Qualcomm Inc. and On Semiconductor Corp., each of which saw high levels of growth based on a combination of organic expansion and key acquisitions, IHS said.
In recent years, South Korea's Samsung Electronics Co. Ltd. had been getting closer to overtaking Intel and becoming the No. 1 chip supplier. But in 2011, Intel lengthened its lead over Samsung, which accounted for 9.2 percent of overall chip sales, unchanged from 2010, IHS said.
Based on the final numbers, IHS said the chip market grew by a paltry 1.3 percent in 2011, down from an earlier estimate by the firm of 1.9 percent growth. A sequential decline of 5.9 percent in the fourth quarter of 2011 pulled the full-year results down, IHS said.
Qualcomm grew 41.6 percent in 2011 to became the sixth largest chip vendor by sales, up from ninth in 2010, IHS said. Qualcomm accounted for 3.3 percent of overall chip sales, just behind No. 5 player Renesas Electronics Corp., which had 3.4 percent, according to IHS.
On Semi moved to No. 18 in chip sales in 2011, up from No. 26 in 2010, the largest jump of any vendor in the top 25, IHS said. Light-emitting diode (LED) maker Nichia Corp ranked No. 23 in chip sales in 2011, thanks to 34 percent growth, IHS said.
In 2011, just over half of 302 chip suppliers tracked by IHS grew sales compared with 2010, IHS said.
Overall, companies headquartered in the Americas saw the greatest improvement to their semiconductor revenues among all regions, at 7.5 percent growth, IHS said. In comparison, revenue fell 7.2 percent as a whole for Japanese firms, which suffered from the impact of the 2011 earthquake, according to the firm.
Nvidia: TSMC 20nm Essentially Worthless
TSMC is having problems with 20nm process, while Intel and Samsung don't appear to have these problems. Is running their own fabs giving Intel and Samsung key yield and cost benefits?
Ron Maltiel
Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless
http://www.extremetech.com/computing/123529-nvidia-deeply-unhappy-with-tsmc-claims-22nm-essentially-worthless
By Joel Hruska on March 23, 2012
One of the unspoken rules of customer-foundry relations is that you virtually never see the former speak poorly of the latter. Only when things have seriously hit the fan do partners like AMD or Nvidia admit to manufacturing problems, and typically only after postponed launches and poor availability have made protestations that everything is fine unsustainable.
That’s why we were surprised — and our source testified to being stunned — that Nvidia gave the following presentation at the International Trade Partner Conference (ITPC) forum last November. Many of the company’s complaints regarding its current partnership with TSMC are exactly what you’d expect given the manufacturing problems the entire industry is facing. What’s surprising are Nvidia’s remarks concerning TSMC’s current cost curves and manufacturing ramps. This is normally the sort of information discussed quietly between a foundry and its customers or by the press with help from various anonymous sources. Discussing the problems publicly is a sign of just how frustrated the company has become.
Watch the underlines for emphasis
TSMC builds hardware for a huge number of companies, but those customers have very different needs and use a wide range of process technologies. Historically, Nvidia (and ATI/AMD) have been regular early adopters. The nature of graphics is that it can easily soak up new processes and the higher transistor counts they enable.
Kepler broke the exponential rise in transistors per GPU
The flip side of that situation is that companies like AMD and Nvidia have also been responsible for assuming the risks associated with “risk production” and footing a hefty bill for the privilege. As those risks mount and costs skyrocket, Nvidia is increasingly unhappy with being asked to shoulder the burden. Nvidia’s slides talk about the need for “real” understanding, compromises on “rough justice,” and a closer relationship that looks more like that of an IDM (Integrated Device Manufacturer). For those of you who don’t know the term, Intel is an IDM — it handles both manufacturing and design. AMD used to be.
When AMD spun GlobalFoundries off, one of the things GF promised to provide that would distinguish it from TSMC was high levels of IDM-style integration. At TSMC, the customization work that is available is highly monetized; specialized work is expensive and time-consuming. In reality, GF’s ability to provide the amount of IDM-like flexibility that it wanted to offer has been sharply constrained by the problems associated with Llano and Bulldozer; our sources tell us that the foundry devoted enormous resources to bringing AMD’s 32nm APU back on track.
According to Nvidia, the current model is unsustainable. Here’s the company’s projected analysis for transistor costs at current and new nodes.
As the process nodes shrink, it takes longer and longer for the cost-per-transistor to fall below the previous generation. At 20nm, the gains all-but vanish. Want to know why Nvidia rearchitected Fermi with a new emphasis on efficiency and performance/watt? You’re looking at the reason. If per-transistor costs remain constant, the only way to improve your cost structure is to make better use of the transistors you’ve got.
As for wafer costs, they’ve become part of the problem.
What this slide states — we can’t even call it a suggestion — is that smaller processes no longer improve yields by leading to a greater number of chips per wafer. Instead, the complexities and difficulties of manufacturing at the new process create a cost structure that provides precious little incentive to manufacture at the new process.
If openly criticizing a foundry partner is unusual, showing data that suggests that your foundry partner can’t provide a cost-effective strategy for building hardware at next-generation process nodes is… a few steps past that point. The recent launch of the GTX 680, and that card’s trifecta of price/performance/power-efficiency actually strengthens the impact of this data. NV would’ve had a good idea how the GK104 was shaping up when it spoke at ITPC in November; this isn’t a case where a company is angry about the performance of a particular part and looking for someone to blame.
Again, follow the underlines.
The GK104 is great, but it doesn’t change the nature or severity of the underlying problems. As for whether Nvidia’s unhappiness with TSMC heralds a potential alliance with GlobalFoundries, we’re dubious. Not only has GF only recently ironed out its own 28nm issues, the nature of the foundry business doesn’t allow for quick shifts. Indeed, part of the reason that manufacturers like TSMC have historically exercised such control over their partners’ PR releases is because once you’ve committed to a foundry, you’re locked in for a substantial period of time. The fact that there’s now two foundries available with cutting-edge technology doesn’t change that, and the Common Platform Alliance favored by IBM, Samsung, and GloFo only mitigates some of the problems with moving a design from foundry to foundry, it doesn’t remove them.
The real question, at least for TSMC’s other customers, is whether the graphs and charts Nvidia has shown are specific to the company’s own products or reflect universal trends. There’s good reason to suspect the latter; Nvidia may have had more trouble than some of TSMC’s other customers, but our analysis of semiconductor industry roadmaps revealed a great deal of uncertainty about the road forward. Nvidia opted to aggressively optimize GK104 precisely because the old strategy of bolting on more cores and ratcheting up transistor counts isn’t sustainable.
Further evidence for the accuracy of NV’s presentation comes, ironically, from the company’s primary GPU competitor. At AMD’s Financial Analyst Day, CEO Rory Read made a point of saying that the company no longer intends to aggressively transition to new process nodes given the diminishing marginal returns from doing so.
Change the color scheme, and Nvidia’s graphs could’ve dropped right into AMD’s presentations in early February.
Nvidia’s willingness to stand up and talk about these problems is an “Emperor’s new clothes” sort of moment. The long-term repercussions, if any, are still unclear.
Ron Maltiel
Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless
http://www.extremetech.com/computing/123529-nvidia-deeply-unhappy-with-tsmc-claims-22nm-essentially-worthless
By Joel Hruska on March 23, 2012
One of the unspoken rules of customer-foundry relations is that you virtually never see the former speak poorly of the latter. Only when things have seriously hit the fan do partners like AMD or Nvidia admit to manufacturing problems, and typically only after postponed launches and poor availability have made protestations that everything is fine unsustainable.
That’s why we were surprised — and our source testified to being stunned — that Nvidia gave the following presentation at the International Trade Partner Conference (ITPC) forum last November. Many of the company’s complaints regarding its current partnership with TSMC are exactly what you’d expect given the manufacturing problems the entire industry is facing. What’s surprising are Nvidia’s remarks concerning TSMC’s current cost curves and manufacturing ramps. This is normally the sort of information discussed quietly between a foundry and its customers or by the press with help from various anonymous sources. Discussing the problems publicly is a sign of just how frustrated the company has become.
Watch the underlines for emphasis
TSMC builds hardware for a huge number of companies, but those customers have very different needs and use a wide range of process technologies. Historically, Nvidia (and ATI/AMD) have been regular early adopters. The nature of graphics is that it can easily soak up new processes and the higher transistor counts they enable.
The flip side of that situation is that companies like AMD and Nvidia have also been responsible for assuming the risks associated with “risk production” and footing a hefty bill for the privilege. As those risks mount and costs skyrocket, Nvidia is increasingly unhappy with being asked to shoulder the burden. Nvidia’s slides talk about the need for “real” understanding, compromises on “rough justice,” and a closer relationship that looks more like that of an IDM (Integrated Device Manufacturer). For those of you who don’t know the term, Intel is an IDM — it handles both manufacturing and design. AMD used to be.
According to Nvidia, the current model is unsustainable. Here’s the company’s projected analysis for transistor costs at current and new nodes.
As the process nodes shrink, it takes longer and longer for the cost-per-transistor to fall below the previous generation. At 20nm, the gains all-but vanish. Want to know why Nvidia rearchitected Fermi with a new emphasis on efficiency and performance/watt? You’re looking at the reason. If per-transistor costs remain constant, the only way to improve your cost structure is to make better use of the transistors you’ve got.
As for wafer costs, they’ve become part of the problem.
What this slide states — we can’t even call it a suggestion — is that smaller processes no longer improve yields by leading to a greater number of chips per wafer. Instead, the complexities and difficulties of manufacturing at the new process create a cost structure that provides precious little incentive to manufacture at the new process.
If openly criticizing a foundry partner is unusual, showing data that suggests that your foundry partner can’t provide a cost-effective strategy for building hardware at next-generation process nodes is… a few steps past that point. The recent launch of the GTX 680, and that card’s trifecta of price/performance/power-efficiency actually strengthens the impact of this data. NV would’ve had a good idea how the GK104 was shaping up when it spoke at ITPC in November; this isn’t a case where a company is angry about the performance of a particular part and looking for someone to blame.
The GK104 is great, but it doesn’t change the nature or severity of the underlying problems. As for whether Nvidia’s unhappiness with TSMC heralds a potential alliance with GlobalFoundries, we’re dubious. Not only has GF only recently ironed out its own 28nm issues, the nature of the foundry business doesn’t allow for quick shifts. Indeed, part of the reason that manufacturers like TSMC have historically exercised such control over their partners’ PR releases is because once you’ve committed to a foundry, you’re locked in for a substantial period of time. The fact that there’s now two foundries available with cutting-edge technology doesn’t change that, and the Common Platform Alliance favored by IBM, Samsung, and GloFo only mitigates some of the problems with moving a design from foundry to foundry, it doesn’t remove them.
The real question, at least for TSMC’s other customers, is whether the graphs and charts Nvidia has shown are specific to the company’s own products or reflect universal trends. There’s good reason to suspect the latter; Nvidia may have had more trouble than some of TSMC’s other customers, but our analysis of semiconductor industry roadmaps revealed a great deal of uncertainty about the road forward. Nvidia opted to aggressively optimize GK104 precisely because the old strategy of bolting on more cores and ratcheting up transistor counts isn’t sustainable.
Further evidence for the accuracy of NV’s presentation comes, ironically, from the company’s primary GPU competitor. At AMD’s Financial Analyst Day, CEO Rory Read made a point of saying that the company no longer intends to aggressively transition to new process nodes given the diminishing marginal returns from doing so.
Change the color scheme, and Nvidia’s graphs could’ve dropped right into AMD’s presentations in early February.
Nvidia’s willingness to stand up and talk about these problems is an “Emperor’s new clothes” sort of moment. The long-term repercussions, if any, are still unclear.
Friday, March 23, 2012
Moore's Law Slowwwing
Below is another example of the end of Moore's law.
See also earlier post.
Ron Maltiel
Feature dimension reduction slowdown
http://www.eetimes.com/discussion/other/4238315/Feature-dimension-reduction-slowdown
Handel Jones , 3/20/2012 12:32 AM EDT
The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase. The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase.
1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.
2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.
3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.
Figure 1- Cost per gate.
With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.
4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.
EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.
New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.
What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.
After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.
The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.
Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.
See also earlier post.
Ron Maltiel
Feature dimension reduction slowdown
http://www.eetimes.com/discussion/other/4238315/Feature-dimension-reduction-slowdown
Handel Jones , 3/20/2012 12:32 AM EDT
The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase. The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase.
1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.
2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.
3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.
Figure 1- Cost per gate.
With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.
4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.
EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.
New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.
What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.
After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.
The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.
Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.
Thursday, March 22, 2012
New iPad-Teardown: Why Apple's A5X uses 45nm
The new iPad processor A5X is about 36% larger than the A5 processor of the previous iPad generation. Both the A5x and the A5 are using 45nm process. This was likely designed in order to get the largest number of working dies from each wafer. Apple will probably do a shrink to the 32nm process when the process becomes more mature. The process shrink will have the benefits of lower power usage which will reduce iPad over-heating and will increase battery time.
It is interesting that while intel already uses 32nm, Apple still uses Samsung's at 45nm.
"A5X measures roughly 163 square millimeters, compared to about 120 square millimeters for the standard A5. Both chips use identical ARM processor cores, but the A5X adds four PowerVR SGX543MP4 graphics cores, which are paired in groups of two and then symmetrically opposed to each other on the floor plan.
The A5X, like the standard A5, features two application processor cores and operates at 1 GHz., UBM TechInsights said. But the A5X includes more DDR interfaces and more architecture added for the handling of quad-core GPU..."
The beefed up DRAM memory interface and the increased graphic processing power is required for the enhanced display of the new iPad.
Ron Maltiel
The New iPad - Generation 3 Teardown and Apple A5X IC Analysis
http://ubmtechinsights.com/teardowns/new-apple-ipad-gen3-teardown-analysis/
Since its introduction almost nearly two years ago, the iPad not only ushered in a new age of consumer electronics by bringing visibility to the ‘tablet’ product, but it also quickly dominated its market. By the end of 2010, Apple had sold over 15 million iPads and, despite strong competition from products released by Motorala and Samsung, held a 75% share of overall sales of tablets.
Approximately one year later, Apple introduced the iPad 2 to much fanfare. Improving on the original, Apple increased the processor power with the introduction of the Apple A5 dual-core processor. As expected by many, the iPad 2 also sold in the millions of units.
Apple had begun a pattern of lifecycles for iPads, so it was no surprise on March 7th that the third generation of the iPad (referred to by Apple as the “new iPad” or “the iPad 3” by others to avoid confusion) was announced. Building upon Apple’s history of iterative improvements in new products, the new iPad boasted of a new Retina display (with 2048 x 1536 resolution, 3.1 total million pixels and 264 pixels per inch) promising the most vibrant iPad to date, a 5 MP backside illuminated sensor that would make the iPad comparable to high-end digital cameras, and the introduction of a brand new processor, the Apple A5X. The new iPad, or iPad 3, was also the first Apple device to the LTE-enabled (or 4G), marking Apple’s first foray into the fastest wireless baseband spectrum available.
When we picked up the device on March 16th, we took it to our lab as soon as we could to take it apart and analyze what makes the new iPad, or iPad 3, different from its predecessors. Of note, was the understanding that some major semiconductor manufacturers were going to walk out with some major design wins, as a product that’s expected to sell in the tens of millions should obviously help their bottom line. The first major design winner in the new Apple iPad is a long time partner in Broadcom. Broadcom picked up three major design wins, two of which for their touchscreen controllers (the BCM5974, which have been found in the iPad 2 and the BCM5973 which was found in the previous iPads and the 1st generation of the iPhone). The other major design win comes for their four-in-one combo wireless chip, the BCM4330, which was also found in the iPhone 4S. Below are some images of the Broadcom ICs we’ve analyzed using our de-encapsulation (decap) process.
Broadcom ICs
A closer look inside the Qualcomm MDM9600 and their other design wins
Qualcomm was another major design winner. Qualcomm has benefitted greatly from Apple’s move into the CDMA market (such as when they introduced the Verizon iPhone 4). When Apple made the decision to offer CDMA versions of their product, it gave Qualcomm the foot in the door it needed to usurp Infineon as the baseband/wireless transceiver provider for them. Since the CDMA iPhone 4, Qualcomm has gotten design wins in the iPad 2 and became the sole IC provider for the iPhone 4S. With the new iPad, Qualcomm gets its LTE Chipset, the MDM9600 designed into it. Qualcomm also provides the RTR8600 transceiver chipset and the PM8028 power management IC. The PM8028 was found within the iPhone 4S whereas the RTR8600 is a major design coup for Qualcomm, replacing the socket that was once held by Infineon/Intel. With the RTR8600, Qualcomm has officially replaced each socket previously held by Infineon/Intel.
The Qualcomm MDM9600 measures in at a die size of approximately 89.89 mm². This LTE Chipset from Qualcomm’s “Gobi” family of embedded data connectivity platforms is compatible across CDMA, HSPA+ and LTE bands and meets Apple’s needs of having a modem that can switch between 3G and 4G seamlessly.
Qualcomm PM8028
Qualcomm RTR8600
Other devices of interest
Apple is well-known for branding IC’s with their recognizable trademark. Either in an effort to prevent competitors from learning about their design selections, or agreements they have in place with manufacturers, Apple devices tend to have components where the manufacturer is not easily determined. Fortunately, due to our decap process, we can find out the secrets inside these chips.
Apple 338S0987 – Cirrus Logic CLI1560B0 Audio CODEC
This device was also found within the iPhone 4S and continues Cirrus Logic’s relationship with the Apple that began back with the Apple iPhone 3GS.
The Image Sensors
In a surprising discovery, both image sensors found in the new iPad were developed by Omnivision.
Omnivision provides the OV297AA 0.3 MP camera and the OV290B 5 MP Backside Illumination Camera Module.
Power Management
Finally, confirmed within the new Apple iPad, is another design win for Dialog. The D1974 power management unit makes it the third unique PMU to be used in each generation of iPad.
The Memory
Hynix H2DTDG8UD1MYR – 16GB of NAND Flash Memory Package
Apple is known for multi-sourcing its manufacturers of Flash for their products. It could very well be Toshiba in one iPad and Samsung in another. In the case of our iPad, we see the same NAND Flash that we also found in the 16GB model of the iPad 2 from Hynix. This memory package features two 64 Gbit dies to equal 16 GBytes of memory.
The same can be said about other system memory. Other teardowns of the new iPad have shown memory packages from Toshiba. In our iPad, we discovered a Micron multichip memory package. The same case exists for the DDR2 SDRAM that comprises the system memory. Some iPads have seen Elpida devices to make up the 1 GB of Low Power DDR2. Our iPad features Samsung memory. Considering the amount of litigation taking place between Samsung and Apple these days, it’s still surprising how such fierce rivals at the product level can work together at the semiconductor level. All this indicates that Apple has taken a strategy of using multiple suppliers from multiple regions to prepare for any difficulty that could arise in their supply chain. Prior to his appointment as CEO, Tim Cook was well known amongst Apple’s employees for his proactive approach to the Supply Chain. That influence still exists today as seen in the new iPad.
The Others
Other major design winners include Skyworks with two major socket wins for their FEMs, Triquint Semiconductor with one win for their power amplifier modules, and Texas Instruments with two socket wins that support the touchscreen. One surprise design winner was Fairchild Semiconductor, who found two of their MOSFET components within the new iPad.
Feature Specs
Apple A5X Processor - Dual-core applications processor with quad-core graphics processor
Retina display - 2048 x 1536 resolution, 3.1 total million pixels, 264 pixels per inch
5 MP backside illuminated sensor - 5-element lens, IR filter, and ISP built into the A5X chip
1080p video recording
4G LTE
Microphone for voice dictation
Primary Component Listing
Broadcom BCM4330 – Bluetooth 4.0, Dual-Band WLAN, FM Transceiver
Broadcom BCM5973 - Touchscreen Controller
Texas Instruments CD3240B0 - Touchscreen Line Driver
Broadcom BCM5974 – Capacitive Touchscreen Controller
Qualcomm PM8028 – Power Management IC
Qualcomm RTR8600 – GSM / CDMA / W-CDMA / LTE Transceiver + GPS chipset
Triquint TQM7M5013 – Gobi Single-mode Modem
Qualcom PM8028 – Quad-Band GSM / GPRS / EDGE-Linear Power Amplifier Module
Qualcomm MDM9600 - LTE Modem Chipset
Apple 338S0987 - Cirrus Logic CLI1560B0 – Audio CODEC
Inside the Apple A5X
Inside the new Apple iPad, or iPad 3, lies a modified A5 processor dubbed the A5X. This modified A5 processor still features two application processor cores and operates at 1 GHz, however, the architecture has been modified to include quad-core graphics. It is stated by Apple to feature the PowerVR SGX543MP4 GPU (the same graphics processor core found in the Playstation Vita). From our decap, right away, you can see that the A5X processor is larger in area than its predecessor. The distinctive die mark also matches that of Samsung-manufactured devices indicating that, once again, Apple has decided to partner with its tablet adversary.
A5X Processor Floorplan
A5 Processor Floorplan
It is interesting that while intel already uses 32nm, Apple still uses Samsung's at 45nm.
"A5X measures roughly 163 square millimeters, compared to about 120 square millimeters for the standard A5. Both chips use identical ARM processor cores, but the A5X adds four PowerVR SGX543MP4 graphics cores, which are paired in groups of two and then symmetrically opposed to each other on the floor plan.
The A5X, like the standard A5, features two application processor cores and operates at 1 GHz., UBM TechInsights said. But the A5X includes more DDR interfaces and more architecture added for the handling of quad-core GPU..."
The beefed up DRAM memory interface and the increased graphic processing power is required for the enhanced display of the new iPad.
Ron Maltiel
The New iPad - Generation 3 Teardown and Apple A5X IC Analysis
http://ubmtechinsights.com/teardowns/new-apple-ipad-gen3-teardown-analysis/
Since its introduction almost nearly two years ago, the iPad not only ushered in a new age of consumer electronics by bringing visibility to the ‘tablet’ product, but it also quickly dominated its market. By the end of 2010, Apple had sold over 15 million iPads and, despite strong competition from products released by Motorala and Samsung, held a 75% share of overall sales of tablets.
Approximately one year later, Apple introduced the iPad 2 to much fanfare. Improving on the original, Apple increased the processor power with the introduction of the Apple A5 dual-core processor. As expected by many, the iPad 2 also sold in the millions of units.
Apple had begun a pattern of lifecycles for iPads, so it was no surprise on March 7th that the third generation of the iPad (referred to by Apple as the “new iPad” or “the iPad 3” by others to avoid confusion) was announced. Building upon Apple’s history of iterative improvements in new products, the new iPad boasted of a new Retina display (with 2048 x 1536 resolution, 3.1 total million pixels and 264 pixels per inch) promising the most vibrant iPad to date, a 5 MP backside illuminated sensor that would make the iPad comparable to high-end digital cameras, and the introduction of a brand new processor, the Apple A5X. The new iPad, or iPad 3, was also the first Apple device to the LTE-enabled (or 4G), marking Apple’s first foray into the fastest wireless baseband spectrum available.
When we picked up the device on March 16th, we took it to our lab as soon as we could to take it apart and analyze what makes the new iPad, or iPad 3, different from its predecessors. Of note, was the understanding that some major semiconductor manufacturers were going to walk out with some major design wins, as a product that’s expected to sell in the tens of millions should obviously help their bottom line. The first major design winner in the new Apple iPad is a long time partner in Broadcom. Broadcom picked up three major design wins, two of which for their touchscreen controllers (the BCM5974, which have been found in the iPad 2 and the BCM5973 which was found in the previous iPads and the 1st generation of the iPhone). The other major design win comes for their four-in-one combo wireless chip, the BCM4330, which was also found in the iPhone 4S. Below are some images of the Broadcom ICs we’ve analyzed using our de-encapsulation (decap) process.
Broadcom ICs
A closer look inside the Qualcomm MDM9600 and their other design wins
Qualcomm was another major design winner. Qualcomm has benefitted greatly from Apple’s move into the CDMA market (such as when they introduced the Verizon iPhone 4). When Apple made the decision to offer CDMA versions of their product, it gave Qualcomm the foot in the door it needed to usurp Infineon as the baseband/wireless transceiver provider for them. Since the CDMA iPhone 4, Qualcomm has gotten design wins in the iPad 2 and became the sole IC provider for the iPhone 4S. With the new iPad, Qualcomm gets its LTE Chipset, the MDM9600 designed into it. Qualcomm also provides the RTR8600 transceiver chipset and the PM8028 power management IC. The PM8028 was found within the iPhone 4S whereas the RTR8600 is a major design coup for Qualcomm, replacing the socket that was once held by Infineon/Intel. With the RTR8600, Qualcomm has officially replaced each socket previously held by Infineon/Intel.
The Qualcomm MDM9600 measures in at a die size of approximately 89.89 mm². This LTE Chipset from Qualcomm’s “Gobi” family of embedded data connectivity platforms is compatible across CDMA, HSPA+ and LTE bands and meets Apple’s needs of having a modem that can switch between 3G and 4G seamlessly.
Qualcomm PM8028
Qualcomm RTR8600
Other devices of interest
Apple is well-known for branding IC’s with their recognizable trademark. Either in an effort to prevent competitors from learning about their design selections, or agreements they have in place with manufacturers, Apple devices tend to have components where the manufacturer is not easily determined. Fortunately, due to our decap process, we can find out the secrets inside these chips.
Apple 338S0987 – Cirrus Logic CLI1560B0 Audio CODEC
This device was also found within the iPhone 4S and continues Cirrus Logic’s relationship with the Apple that began back with the Apple iPhone 3GS.
The Image Sensors
In a surprising discovery, both image sensors found in the new iPad were developed by Omnivision.
Omnivision provides the OV297AA 0.3 MP camera and the OV290B 5 MP Backside Illumination Camera Module.
Power Management
Finally, confirmed within the new Apple iPad, is another design win for Dialog. The D1974 power management unit makes it the third unique PMU to be used in each generation of iPad.
The Memory
Hynix H2DTDG8UD1MYR – 16GB of NAND Flash Memory Package
Apple is known for multi-sourcing its manufacturers of Flash for their products. It could very well be Toshiba in one iPad and Samsung in another. In the case of our iPad, we see the same NAND Flash that we also found in the 16GB model of the iPad 2 from Hynix. This memory package features two 64 Gbit dies to equal 16 GBytes of memory.
The same can be said about other system memory. Other teardowns of the new iPad have shown memory packages from Toshiba. In our iPad, we discovered a Micron multichip memory package. The same case exists for the DDR2 SDRAM that comprises the system memory. Some iPads have seen Elpida devices to make up the 1 GB of Low Power DDR2. Our iPad features Samsung memory. Considering the amount of litigation taking place between Samsung and Apple these days, it’s still surprising how such fierce rivals at the product level can work together at the semiconductor level. All this indicates that Apple has taken a strategy of using multiple suppliers from multiple regions to prepare for any difficulty that could arise in their supply chain. Prior to his appointment as CEO, Tim Cook was well known amongst Apple’s employees for his proactive approach to the Supply Chain. That influence still exists today as seen in the new iPad.
The Others
Other major design winners include Skyworks with two major socket wins for their FEMs, Triquint Semiconductor with one win for their power amplifier modules, and Texas Instruments with two socket wins that support the touchscreen. One surprise design winner was Fairchild Semiconductor, who found two of their MOSFET components within the new iPad.
Feature Specs
Apple A5X Processor - Dual-core applications processor with quad-core graphics processor
Retina display - 2048 x 1536 resolution, 3.1 total million pixels, 264 pixels per inch
5 MP backside illuminated sensor - 5-element lens, IR filter, and ISP built into the A5X chip
1080p video recording
4G LTE
Microphone for voice dictation
Primary Component Listing
Broadcom BCM4330 – Bluetooth 4.0, Dual-Band WLAN, FM Transceiver
Broadcom BCM5973 - Touchscreen Controller
Texas Instruments CD3240B0 - Touchscreen Line Driver
Broadcom BCM5974 – Capacitive Touchscreen Controller
Qualcomm PM8028 – Power Management IC
Qualcomm RTR8600 – GSM / CDMA / W-CDMA / LTE Transceiver + GPS chipset
Triquint TQM7M5013 – Gobi Single-mode Modem
Qualcom PM8028 – Quad-Band GSM / GPRS / EDGE-Linear Power Amplifier Module
Qualcomm MDM9600 - LTE Modem Chipset
Apple 338S0987 - Cirrus Logic CLI1560B0 – Audio CODEC
Inside the Apple A5X
Inside the new Apple iPad, or iPad 3, lies a modified A5 processor dubbed the A5X. This modified A5 processor still features two application processor cores and operates at 1 GHz, however, the architecture has been modified to include quad-core graphics. It is stated by Apple to feature the PowerVR SGX543MP4 GPU (the same graphics processor core found in the Playstation Vita). From our decap, right away, you can see that the A5X processor is larger in area than its predecessor. The distinctive die mark also matches that of Samsung-manufactured devices indicating that, once again, Apple has decided to partner with its tablet adversary.
A5X Processor Floorplan
A5 Processor Floorplan
Wednesday, March 21, 2012
Are Japan's Fabs stuck above 28nm Process Technology?
One of the casualties of the $10 Billion cost of developing new semiconductor technologies is Japan's semiconductor industry as is detailed below.
Ron Maltiel
Japan's aging semiconductor industry revealed by 2011 earthquake
http://www.electroiq.com/articles/sst/2012/03/japans-aging-semiconductor-industry-revealed-by-2011-earthquake.html
March 20, 2012 -- One year ago, Japan's semiconductor industry was rocked by a devastating earthquake and tsunami. However, the real disaster for Japan's chip industry occurred during the years before the earthquake -- a period when the country lost its status as one of the world's leading semiconductor manufacturing regions, according to the IHS iSuppli Semiconductor Value Chain Service.
The limited impact of the quake on the global semiconductor industry dramatically illustrated Japan diminished status in the worldwide chip hierarchy and underscored the pressing need for the country to revitalize its business in this area, said Len Jelinek, director and chief analyst for semiconductor manufacturing at IHS.
Suppliers headquartered in Japan accounted for more than one quarter of global semiconductor revenue in 2003, commanding a 27% share. During the next eight years, Japan's share suffered a general decline, dropping 8 points to 19% in 2011 (see the figure).
Semiconductor Revenue
2003 2004 2005 2006 2007 2008 2009 2010 2011 % of Global
27.0% 25.4% 23.4% 22.3% 23.4% 23.5% 21.4% 20.4% 18.7%
Figure. Share of Global Semiconductor Revenue Held by Suppliers Headquartered in Japan (Share of Global Revenue in U.S. Dollars). SOURCE: IHS iSuppli March 2012.
Of the major global semiconductor manufacturing regions, Japan now has the smallest number of number of advanced 300mm wafer fabs and the largest number of mature 6" wafer fabs. Companies in Japan have resisted the trend of closing mature facilities and either outsourcing manufacturing or rebuilding manufacturing facilities to current state-of-the-art facilities. Once one of the worlds most advanced semiconductor producers, Japans semiconductor manufacturing operations have become senescent relative to the rest of the world.
In the aftermath of the disaster, the immediate concern was that the semiconductor supply chain would grind to a halt. Massive component shortages were predicted with the potential for recovery pushed out as far as a year. However, by most accounts, things are now back to normal. Of the damaged manufacturing facilities, only one operated by Freescale Semiconductor was shut down permanently after the disaster.
Freescale previously had announced that it intended at the end of 2012 to close the fab in Sendai, an older 6-inch facility that originally manufactured analog products. The earthquake simply hastened the closure.
It is now clear that the impact of the earthquake and tsunami on the global semiconductor market fell far short of some prognosticators' dire predictions.
Unfortunately for Japanese semiconductor companies, the disaster uncovered an issue that had been known but not openly acknowledged: Japan is no longer in a leadership position for the manufacturing of semiconductor components. The long-overdue revitalization of the Japanese semiconductor industry has surfaced as the real issue.
In February, a proposal emerged to address Japan's semiconductor industry weakness that called for the consolidation of manufacturing operations at semiconductor giants Renesas, Fujitsu and Panasonic.
The plan separates out design and manufacturing into two separate companies. Furthermore, the proposal calls for a large capital injection to revitalize the manufacturing company.
Sadly, the plan is really a well-disguised roadmap for significant reduction in semiconductor manufacturing.
Can the plan actually lead to the revitalization of wafer manufacturing in Japan? IHS believes it is highly unlikely.
As the leading chip manufacturing companies transition to sub-28-nanometer manufacturing, Japan is facing the fact that it currently has no company capable of volume manufacturing using this advanced technology node. History has shown that success is driven by experience. Without a strong technical platform on which to gain experience and move forward, there is little chance of the country achieving the transition to sub-28-nanometer production.
How will the semiconductor industry reshape itself? Will Japan's focus shift to design?
Only time will determine the answer, but the probability of Japan successfully sustaining its mature manufacturing engine diminishes with each passing day.
Ron Maltiel
Japan's aging semiconductor industry revealed by 2011 earthquake
http://www.electroiq.com/articles/sst/2012/03/japans-aging-semiconductor-industry-revealed-by-2011-earthquake.html
March 20, 2012 -- One year ago, Japan's semiconductor industry was rocked by a devastating earthquake and tsunami. However, the real disaster for Japan's chip industry occurred during the years before the earthquake -- a period when the country lost its status as one of the world's leading semiconductor manufacturing regions, according to the IHS iSuppli Semiconductor Value Chain Service.
The limited impact of the quake on the global semiconductor industry dramatically illustrated Japan diminished status in the worldwide chip hierarchy and underscored the pressing need for the country to revitalize its business in this area, said Len Jelinek, director and chief analyst for semiconductor manufacturing at IHS.
Suppliers headquartered in Japan accounted for more than one quarter of global semiconductor revenue in 2003, commanding a 27% share. During the next eight years, Japan's share suffered a general decline, dropping 8 points to 19% in 2011 (see the figure).
Semiconductor Revenue
2003 2004 2005 2006 2007 2008 2009 2010 2011 % of Global
27.0% 25.4% 23.4% 22.3% 23.4% 23.5% 21.4% 20.4% 18.7%
Figure. Share of Global Semiconductor Revenue Held by Suppliers Headquartered in Japan (Share of Global Revenue in U.S. Dollars). SOURCE: IHS iSuppli March 2012.
Of the major global semiconductor manufacturing regions, Japan now has the smallest number of number of advanced 300mm wafer fabs and the largest number of mature 6" wafer fabs. Companies in Japan have resisted the trend of closing mature facilities and either outsourcing manufacturing or rebuilding manufacturing facilities to current state-of-the-art facilities. Once one of the worlds most advanced semiconductor producers, Japans semiconductor manufacturing operations have become senescent relative to the rest of the world.
In the aftermath of the disaster, the immediate concern was that the semiconductor supply chain would grind to a halt. Massive component shortages were predicted with the potential for recovery pushed out as far as a year. However, by most accounts, things are now back to normal. Of the damaged manufacturing facilities, only one operated by Freescale Semiconductor was shut down permanently after the disaster.
Freescale previously had announced that it intended at the end of 2012 to close the fab in Sendai, an older 6-inch facility that originally manufactured analog products. The earthquake simply hastened the closure.
It is now clear that the impact of the earthquake and tsunami on the global semiconductor market fell far short of some prognosticators' dire predictions.
Unfortunately for Japanese semiconductor companies, the disaster uncovered an issue that had been known but not openly acknowledged: Japan is no longer in a leadership position for the manufacturing of semiconductor components. The long-overdue revitalization of the Japanese semiconductor industry has surfaced as the real issue.
In February, a proposal emerged to address Japan's semiconductor industry weakness that called for the consolidation of manufacturing operations at semiconductor giants Renesas, Fujitsu and Panasonic.
The plan separates out design and manufacturing into two separate companies. Furthermore, the proposal calls for a large capital injection to revitalize the manufacturing company.
Sadly, the plan is really a well-disguised roadmap for significant reduction in semiconductor manufacturing.
Can the plan actually lead to the revitalization of wafer manufacturing in Japan? IHS believes it is highly unlikely.
As the leading chip manufacturing companies transition to sub-28-nanometer manufacturing, Japan is facing the fact that it currently has no company capable of volume manufacturing using this advanced technology node. History has shown that success is driven by experience. Without a strong technical platform on which to gain experience and move forward, there is little chance of the country achieving the transition to sub-28-nanometer production.
How will the semiconductor industry reshape itself? Will Japan's focus shift to design?
Only time will determine the answer, but the probability of Japan successfully sustaining its mature manufacturing engine diminishes with each passing day.
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