Interconnect Issues: History and Future Prospects

Interconnection play a key role in shrinking semiconductor chips, the latest interconnection issues are discussed below:

"The research pipeline of the semiconductor industry involves increasingly radical potential solutions to carry technology advancement through dimensional scaling to beyond-conventional CMOS. Many logic devices are under investigation to extend Moore’s Law to beyond the year 2020. These logic devices differ in structure and operating principles, and include various physical quantities that may be used for encoding information, such as charge, electric dipole, magnetic dipole (spin), orbital state, mechanical position, light intensity, etc. However, any device technology that offers advantages in performance, power dissipation or ease in dimensional scaling will have to be complemented with an interconnect technology that offers similar trades to avoid major bottlenecks due to interconnects. Various carbon-based interconnects were shown to have comparable or better performance compared to Cu/low-k in terms of both resistance-capacitance (rc) product and energy-delay-product."

 

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

 

See an earlier article below

Interconnect Issues: History and Future Prospects, Part 2

Ahmet Ceyhan, Azad NaeemiGeorgia Institute of Technology

The research pipeline of the semiconductor industry involves increasingly radical potential solutions to carry technology advancement through dimensional scaling to beyond-conventional CMOS. Many logic devices are under investigation to extend Moore's Law to beyond the year 2020. These logic devices differ in structure and operating principles, and include various physical quantities that may be used for encoding information, such as charge, electric dipole, magnetic dipole (spin), orbital state, mechanical position, light intensity, etc.[1] However, any device technology that offers advantages in performance, power dissipation or ease in dimensional scaling will have to be complemented with an interconnect technology that offers similar trades to avoid major bottlenecks due to interconnects, which were described in [2]. Various carbon-based interconnects were shown to have comparable or better performance compared to Cu/low-k in terms of both resistance-capacitance (rc) product and energy-delay-product (EDP).[2]

 

The aim of this article is to investigate the interactions of interconnects with various voltage-controlled, charge-based devices similar to the conventional Si-CMOS transistor, including high-performance and ultra-low-power options. For that purpose, we pair finFETs, MOSFET-like carbon nanotube FETs (CNFETs), homojunction III-V tunnel FETs (TFETs) and sub-threshold CMOS devices with conventional Cu/low-k and emerging interconnect options; and we compare the relative performances at the circuit level. These device and interconnect technology options are illustrated in Figure 1. Since various device technologies offer very different characteristics in terms of the output current, input capacitance, subthreshold swing, etc., the constraints that they put on interconnects and the best interconnect option for each device are different as well.

 

This difference stems from the fact that the impacts of technology parameters of various interconnect technologies on the speed and energy advantages of a circuit may differ depending on the transistors used. Emerging carbon nanotube (CNT) and graphene nanoribbon (GNR) interconnects are mostly more resistive than Cu/low-k [3,4], but they offer lower capacitances.

 

Based on the Berkeley Short-channel IGFET Common Gate Model (BSIM-CMG),[5] predictive technology models (PTMs) for finFET devices are developed jointly by the Arizona State University PTM Group and ARM.[6] The development of the model parameters for the BSIM-CMG model is performed using the scaling theory of multi-gate devices, physical models and ITRS projections. Compared to planar bulk CMOS devices, finFET devices have significantly improved short channel effects (SCE) due to better electrostatics, can carry more current and offer improved area efficiency. The channel width is quantized; hence, the number of fins has to be optimized for drive current choices.

 

CNFET devices are alternative solutions to performance enhancement of transistors in the "atomic dimension limit" beyond 2020. A compact model developed by Deng et al.[7] is calibrated to meet reasonable ON current requirements while controlling the threshold voltage to keep leakage current at a reasonable value; and used for simulating MOSFET-like CNFET gates at the 16 nm technology node to predict the circuit- and system-level properties of CNFET devices. This model includes various non-idealities, such as the quantum confinement effects on both circumferential and axial directions, elastic scattering in the channel region, the resistive source/drain, the Schottky-barrier resistance, the acoustical and phonon scattering in the channel region, the screening effect by the parallel CNTs in CNFETs that contain multiple parallel CNTs under the same gate, and parasitic gate capacitances. The rest of both articles

 

 

While FinFET Charging Ahead, Other 20nm challenges

While the industry is following Intel's lead with FinFET transistors, there are several additional major problems in continuing semiconductors technology scaling. Some key problems are discussed below.

More on 22nm challenges.

Ron Maltiel



Top Five Design and Manufacturing Challenges at 20nm

http://semimd.com/blog/2012/03/21/top-five-design-and-manufacturing-challenges-at-20nm/
By Mark LaPedus

The hottest topic in the leading-edge silicon foundry world centers around the shift from planar transistors to finFET structures at the 14nm process node.

GlobalFoundries, Samsung, TSMC and UMC are racing each other to develop finFETs at the 14nm node. But the industry is getting ahead of itself, as experts warn there are still enormous IC design and manufacturing challenges at the 20nm process node. The foundries will continue to use planar transistor structures at 28nm and 20nm, with plans to move to finFETs at 14nm.

Some but not all foundries are still struggling to ramp up their processes based on high-k/metal-gate schemes at the 28nm node. While vendors are seeing various challenges at 28nm, the 20nm node is expected to be even more daunting. “It’s a brave new world at 20nm,” said Tom Beckley, senior vice president of research and development for custom IC and signoff for the Silicon Realization Group at Cadence Design Systems Inc.

At 20nm, there are also economic factors involved, namely fab, process and design costs. And there are also technology challenges, such as the advent of double patterning, severe layout-dependent effects, as well as the introduction of a new and third layer of local interconnect in the design.

That layer — or the so-called middle of the line (MOL) — will likely become “disruptive” in the IC flow, said Luigi Capodieci, director of DFM/CAD and R&D Fellow at silicon foundry vendor GlobalFoundries Inc. Capodieci and Beckley were among the keynoters at the 13th International Symposium on Quality Electronic Design (ISQED) in Santa Clara, Calif. on Tuesday (March 20).

There are a multitude of design and manufacturing challenges at the 20nm node. Based on the keynote presentations from the two design/foundry experts at ISQED, here are five of the bigger design/manufacturing challenges — and trends — at 20nm:


1. The economics factors favor a select few

Chip scaling enables smaller devices at lower costs, but there are also some major ramifications: Fewer and fewer vendors can participate as the industry marches down to the smaller nodes. Only the players with deep pockets can afford to play at 20nm. It’s simply becoming too expensive for most to play at the bleeding-edge of IC design and manufacturing.

The foundries are seeing a clear trend at the leading-edge. “The number of tape outs is decreasing, but the volumes are much higher,” said GlobalFoundries’ Capodieci during his keynote at ISQED.

Citing International Business Strategies Inc. (IBS), a research firm, Cadence’s Beckley said at the 32/28nm nodes, a fab runs $3 billion, process R&D is $1.2 billion, IC design costs ranges from $50 million to $90 million, and mask costs are from $2 million to $3 million.

Citing the same research firm, he said at the 22/20nm nodes, a fab will cost $4 billion to $7 billion, process R&D runs from $2.1 billion to $3 billion, design costs run from between $120 million to $500 million, and mask costs are from $5 million to $8 million.

From his own data, he said EDA tool costs in total run from $800 million to $1.2 billion for the 22/20nm nodes, compared to $400 million to $500 million for 32nm/28nm. Another troubling trend is verification. “Verification times are exploding,” he added.

The solution to the problem? In the past, circuit designers and layout engineers lived in separate silos. The two groups will need to collaborate in order to deal with the complexities involved at 20nm and beyond, Beckley said.


2. Double patterning has (unfortunately) entered the spotlight

The IC industry has pushed 193nm wavelength lithography much further than previously thought. Amazingly, on the logic front, the IC industry is using today’s 193nm immersion scanners based on signal-exposure techniques at the 32nm/28nm nodes.

But due to the delays with the various next-generation lithography (NGL) candidates — namely extreme ultraviolet (EUV) — the industry must embrace 193nm lithography and multi-patterning at 20nm and perhaps beyond. Today, Toshiba Corp. and SanDisk Corp. are making 19nm NAND devices using 193nm immersion scanners — and with the help of a resolution enhancement technique (RET) called self-aligned double patterning. Meanwhile, at 22nm, Intel Corp. is using 193nm immersion — with the help of some form of double-patterning technique.

Double pattering involves separate exposures of the same layer using two photomasks, which, in turn, adds complexity and cost in chip manufacturing.

“At 20nm, the foundries will require double-patterning,” said Beckley during his ISQED keynote, but that “brings coloring” into the mix. In double-patterning, the layout patterns are split and decomposed into two masks. The polygons or features are assigned opposite colors.

The question is whether the coloring is managed by the designer or foundry. That process should not be managed by the foundry, he said. “Coloring must be managed within the design methodology and saved as an integral part of the IP,” he said.

At 20nm, the foundries will likely embrace a double-pattering technique that involves “litho-etch-litho-etch (LELE),” said GlobalFoundries’ Capodieci. LELE poses some challenges in terms of the composition/decomposition steps and overlay. “Overlay can cause local line width variations or local space CD variations depending on the process scheme, which translates into electrical degradation,” he said.

At 20nm, GlobalFoundries and its EDA partners are working on adding “double-patterning-aware” technologies to solve many of the issues. To get around many of these issues, the IC industry is banking on extreme ultraviolet (EUV) lithography. But EUV is late and is a question mark for 14nm. The problem continues to be the power source and throughput.

EUV remains the lithography technology for “tomorrow,” said Capodieci. “Tomorrow’s lithography is still happening tomorrow.”

3. New routing layers

At 28nm and above, the manufacturing flow consists of two parts: front-end-of-the-line (FEOL) and backend-of –the-line (BEOL). The FEOL involves the formation of the transistors and logic, while BEOL handles the vias, interconnects and other structures.

At 20nm, the foundries are now talking about a third layer of interconnect. That layer — or MOL — will become another challenge in the manufacturing flow, Capodieci said.

As a result, the industry will require “new methodologies” to address the new routing layer, said Cadence’s Beckley.


4. Severe layout-dependent effects
Beckley said severe layout-dependent effects are expected at all advanced nodes. Shallow trench isolation (STI) and well proximity effect (WPE) are two types of layout-dependent effects. So it is important that vendors get involved “early in the design stage to handle the parasitics,” he said.


5. More DFM to the rescue

Is Moore’s Law slowing down? “The answer is that it is not for the memory and processor IDMs, but definitely for the foundries,” said G. Dan Hutcheson, president of VLSI Research Inc. “The alarming thing about it is that the ability of foundries to convert their process development and tool investments into revenues has been steadily declining since 130nm. The importance of 130nm is that’s when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then.”

Is foundry model falling apart? (Source: VLSI)

”What’s more scary about the chart is that the decline is predictable, forming a steady downward trend,” said Hutcheson. ”Meanwhile, the fabless companies at the leading edge, such as Nvidia and Qualcomm are visibly concerned about their foundries’ ability to keep up with Moore’s Law. To stay in the game they need a steady decline in cost-per-transistor. If anything, this chart certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”

The solution? EDA houses, foundries and fabless chip makers must ”partner more closely,” he said. ”But this comes at a time when the foundries have become more mistrustful, communicating less about upcoming processes. One thing is clear: If these issues don’t get resolved, there will be a major restructuring of the industry.”

Amid these alarming trends, there is also pressure among chip makers to develop more robust designs — and ensure they can be manufactured in a timely fashion. To meet these challenges, IC vendors have recently embraced — and put more emphasis — on DFM. As part of the DFM equation, chips yields — and the yield enhancement process — have become even more critical.

Within that technology, GlobalFoundries has worked with Mentor to develop a flow to boost yields. In another major step to solve the problem, Cadence and GlobalFoundries recently teamed up to reduce the turnaround times for DFM signoff at 28nm. It’s likely that this technology will be migrated to 20nm.

Using Cadence’s “in-design” DFM tools, GlobalFoundries calls the technology DRC+. The core of the DRC+ flow is two-dimensional shape-based pattern matching, which offers speed improvements in error detection and fixing. This technology enables customers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.

In the DFM world, this is a step in the right direction. GlobalFoundries’ Capodieci said the technology is 10,000 times faster than simulations