Wednesday, February 27, 2013

Altera 14nm FPGA Using Intel Foundry

A good move by Intel and Altera. 

Altera said at Morgan Stanley Tech conference: "Intel has die size advantage because it seems very difficult to scale the backend/ interconnect."
Also FPGA are early adopters of bleeding edge Intel has die size advantage because it seems very difficult to scale the backend/ interconnect.
It improves Altera competitive position relative to Xilinx since Intel has ahead in 14nm process manufacturing. Altera would have to tread carefully between Intel and other ARM processor vendors. Altera is guaranteed access for 12 years, I wonder how would they handle capacity and wafer yield crashes.

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Intel to make 14-nm FPGAs for Altera

Rick Merritt, 2/26/2013 1:01 AM EST

Intel will let Altera make FPGAs in its 14nm FinFET process in a deal that turns up the heat on TSMC in foundry and Xilinx in high-end FPGAs. SAN JOSE, Calif. – Intel Corp. will build FPGAs for Altera Corp. using its 14-nm FinFET process technology in a deal that turns up the heat on TSMC in foundry and Xilinx in high-end FPGAs. The deal marks the largest of a string of publicly disclosed foundry deals for Intel to date--and its first at 14 nm--but is not expected to result in products until 2014.

Altera (San Jose, Calif.) declined to disclose details of the deal, including what products it will make when. However, Altera CEO John Daane did say he believes Intel is two to four years ahead of other foundries with its 14-nm FinFET process, which Altera will use initially to give its highest-end FPGAs advantages in density, performance and power.

High-end parts make up about half the FPGA market, with Altera claiming a lead with 40- and 28-nm parts that it aims to extend with the new Intel process. Besides winning more business away from rival Xilinx, the 14-nm parts could help Altera grab more sockets away from ASICs and application-specific standard devices, Daane said.

Intel promised Altera access to the 14-nm process for 12 years to satisfy long-term availability requirements of defense and other customers, Daane said. The multi-year deal allows Altera to use other existing and future nodes, but the FPGA maker initially will focus on high-end parts at 14 nm, he said.

Using multi-die chip stacks, Altera currently ships an FPGA that packs 1.2 million logic elements, lagging a similar chip from Xilinx with 2 million logic elements. However, such parts have relatively high costs and power and take a performance hit due to additional on-chip communications. They are used "for prototyping predominantly—it's a niche," Daane said.

Altera surveyed foundries for a year before striking the deal with Intel. It will continue to make chips at TSMC and conduct ongoing evaluations of other processes as they develop.

Daane cited reports that other foundries are grafting a first-generation of FinFETs on to existing 20-nm design rules to create what they are calling a 14-nm node. "Intel's 14-nm is a second generation FinFET process, while others are just starting to implement their first," he said.

The deal marks "a significant departure for Altera," said Deutsche Bank analyst Ross Seymore, who doesn't expect Altera to see revenue from it until 2015. It is also "a validation of Intel's manufacturing leadership" that "should help Intel make gains in foundry services," he added.

"It is not Intel's objective to become a general foundry service provider," said Len Jelinek, a chief analyst at IHS iSuppli.  Rather it aims "to select a few high volume [foundry] clients [that] provide Intel with an additional revenue stream to help defer the cost of its advanced manufacturing capability," he said. 

Intel says 14-nm node ready this year
To date, Intel has announced it is making chips in its 22-nm FinFET process for two FPGA startups, Achronix and Tablua, and network processor maker Netronome.  Achronix officially started sampling its FPGAs based on Intel's 22-nm technology last week, claiming it is two years ahead of competitors using TSMC.

Unconfirmed reports have said Intel could be making 22-nm ASICs for Cisco. Others said the PC chip giant may be working on a deal to make mobile processors for Apple, which is trying to reduce its foundry dependence on archrival Samsung.

Daane expressed confidence Intel will be able to meet Altera's volume requirements

"Clearly this is a step up for us," said an Intel spokesman. "We were proceeding slowly and cautiously [into the foundry business] and now we are increasing the pace," he said.

Intel will have its 14-nm process in production later this year, the spokesman added. Globalfoundries announced last fall it plans to accelerate its road map, making a 14-nm process available some time in 2014.

The Altera deal "puts Intel out there as a contender in the foundry market," said Joanne  Itow, manufacturing analyst at Semico Research Corp.

Itow noted that TSMC founder Morris Chang listed Intel as a competitor in a recent conference call. Altera will get at least a one or two year advantage using Intel's 14-nm process, Itow said, but she doubted the FPGA maker will be able to ship the parts until sometime in 2014.

Tuesday, February 26, 2013

Thinner Wafers Improve Power IC

Infineon ships power ICs from floppy 300-mm wafers

LONDON –Infineon Technologies AG has claimed it is the first and only company worldwide to produce power semiconductors on 300-millimeter thin wafers and that this will bring the company both a technical and cost advantage over its competition. Infineon (Munich, Germany) has been working on the technology for several years and in February 2013 received first customer clearances to ship CoolMOS family products made on a 300-mm production line at Villach, Austria, which uses thin wafers. The chips are now being shipped worldwide, Infineon said. As power flows vertically in a power MOSFET the reduced thickness lowers resistance and losses and allows heat to be removed more effectively. Infineon has worked with thinned wafers or thin epitaxial structures on top of wafers for more than a decade. However, transferring such a process to 300-mm wafers sets additional challenges. Infineon did not indicate what power ICs are the first to ship from 300-mm wafers but is reported to have been working on power MOSFETs and insulated-gate bipolar transistors (IGBTs). A wafer is typically 350-microns thick prior to being diced into individual chips. At the 200-mm wafer size Infineon typically thins power wafers back to 60-micron and even 40-micron thicknesses. The technology is used for IGBTs) and high-and low-power MOSFETs for a range of applications from automotive engine control through to power packs and induction hobs. The larger size of 300-mm wafer compared to 200-mm wafers used as standard for power IC production means two-and-a-half times as many chips can be made from each one providing a cost advantage to Infineon. "Infineon put its faith in this manufacturing technology very early on and continued to invest even in economically difficult times," said Reinhard Ploss, CEO of Infineon, in a statement. "The qualification of our entire 300-millimeter line represents a veritable leap ahead of the competition," he added. Infineon plans to add the approval of its back-end packaging site in Malacca, Malaysia and then to expand production to its front-end site in Dresden, Germany, where a fully automated 300-mm production line will focus on high volume production. The technology transfer to Dresden is running on schedule and qualification of the first CoolMOS products will be completed in March 2013, Infineon said. Meanwhile Villach will work on transferring more power semiconductor technologies to 300-mm production.

Thursday, February 21, 2013

Next iPhone and iPad MicroProcessor

Soon Apple will introduce a new iPhone and iPad. Who will fabricate the new Apple processor?

Apple is drifting away from Samsung. TSMC is not close to an agreement with Apple. Apple will not shift from their own A processor design to an Intel processor since the A processor gives them unique performance advantages. Intel's growing focus on the tablet market increases their competition with Apple.

A discussion of what will be new on the new processor A7:

"1. Will .. die size plateaus at some point.
2.  Pixel count now stabilized last 2 generations .. added circuit horsepower driving improved performance
3.  Block count evolves..(IP acquisitions of the anobit or authentec) ..."

As I wrote on May 31, 2012, "there is a room for an overall personal computer hierarchy reorganization... Currently in PC/ Mac we have a microprocessor (with some fast DRAM memory) connected to long term storage in flash SSD or HDD.
There would be many benefits to adding a small flash NAND between the microprocessor and the long term storage."

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Wednesday, February 20, 2013

ISSCC 2013: Memory, High-performance Digital, and Wireless trends

Solid State Technology published three articles summarizing ISSCC 2013  technology trends. They "see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash... However, due to the major scaling challenges...continued increase in the use of smart algorithms and error-correction techniques...we see logic processes adopting FinFET devices.

"The relentless march of process technology brings more integration and performance. IBM’s System z processor leads the charge at ISSCC 2013 clocking in at 5.7GHz and with 2.75B transistors."

"Data rates for modern wireless standards are increasing rapidly and this is evident from the trend of cellular standards.The data rate has increased 100X over the last decade and another 10X is projected in the next five years"

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Wednesday, February 13, 2013

Semiconductor Moore's Law Running out of Money

New 14nm process technology and design IP development costs more than $1.5 billion, while new fabs cost several billions. Only very few companies will be able to continue developing and building new fabs. A recent forecast at Common Platform Technology Forum see  +44% growth for foundries.

More stories in March 2012 Moore's Law End? (Next semiconductors gen. cost $10 billion) and Moore's Law Slowwwing .

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Tuesday, February 12, 2013

IBM: Fab Future Beyond FinFETs

The Common Technology Platform and other vendors have been lagging Intel in process development and  integration for several years. In a recent Common Platform Technology Forum, IBM presented their latest effort to catch up - vision of Fab future.
"IBM spotlights double patterning tricks with immersion lithography, showed advances in fully depleted silicon-on-insulator".

 "IBM, GloFo and Samsung now claim they have the lion's share of today's 32/28 nm, high-K metal gate capacity."
While they are claiming to have the fab capacity lead for 28nm HKMG process, Intel, TSMC, and other foundries would feel differently.

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Monday, February 11, 2013

Integrating Flash in DDR4 DIMMs

Micron came up with a new product that adds flash memory on " the DDR4 bus in 18 months... leapfrogging today's solid state drives on PCI Express to open up new applications. ... The move gives flash a new position in the computer memory hierarchy, ahead of todayĆ¢€™s solid state drives that ride the PCI Express bus.
The Hybrid DIMMs will be more expensive than SSDs but likely offer greater performance with memory access times measured in nano- rather than microseconds."
See more

This is an interesting product that leverages the speed of flash and places it higher in a computer system hierarchy. Intel has been working on developing other products that add flash memory closer to the microprocessor (see April 5, 2012 Flash is not just about storage )


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