Monday, November 26, 2012

Preview of 2013 ISSCC

ISSCC Full program

Some highlights from the upcoming ISSCC 2013

1. Revving ReRAMS, boosting memory bandwidth

2. Samsung big.little, but no Intel, Nvidia CPUs

ISSCC preview: Revving ReRAMS, boosting memory bandwidth

Brian Fuller 11/19/2012 9:05 AM EST

SAN FRANCISCO--Relentless scaling advances will highlight memory papers at February's International Solid State Circuits Conference here, but it may be break-throughs in off-beat memory architectures that raise a few eyebrows.
ISSCC, scheduled for Feb. 17-21, 2013 at the Marriott, features a slightly smaller percentage of memory papers than usual for the five-day affair (9 percent of the total is down from 10 percent this year and 10 pecent in 2011), but the topics are no less fascinating.

Memory subcommittee chair Kevin Zhang of Intel notes in his memory overview, "We continue to see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash for very broad applications. However, due to the major scaling challenges in all mainstream memory technologies, we see a continued increase in the use of smart algorithms and error-correction techniques to compensate for increased device variability."
Revving ReRAM

One of the standout papers for the memory sessions comes from Toshiba and Sandisk, who will describe a 32Gb ReRAM (Resistive random-access memory) test chip developed in 24nm process, with a diode as the selection device.

The allure of alternative non-volatile memories has been high cycling capability and lower power per bit in read/write but their densities don't compete with NAND flash. ISSCC organizers noted that the highest density for a single chip published at last year’s ISSCC is 64Mb for ReRAM and 8Gb for PRAM, while NAND can reach up to 128Gb.

The Sandisk-Toshiba test chip is a metal-oxide-based ReRAM is based on 24nm technology node with a diode as the selection device and a 2-layered architecture.....

2. Samsung big.little, but no Intel, Nvidia CPUs
Samsung will describe the first mobile applications processor to use ARM’s big.little concept....

Additional information

Ron Maltiel

Wednesday, November 21, 2012

Samsung Advances Memory Storage eMMC to 1x-nm Process

Samsung unveiled a 64 gigabytes (GB) embedded multimedia card(eMMC) based on 10 nanometer (nm)process technology (see below). Earlier in August Samsung started "volume production of 128-gigabyte (GB) embedded NAND for next-generation smartphones, tablets and other mobile devices, the company said Wednesday (Sept. 19). Samsung began production of the 128-GB embedded multimedia card (eMMC) Pro Class 1500 NAND in late August"

While the announcement of 10nm flash NAND is an important step, this is just an initial step in ramping up the process in the 1xx nm process. We should keep in mind that definition of 10nm class process is a bit loose. It probably just means that it uses a process in the 1x-nanometer class
Ron Maltiel

Additional information

Samsung Advances Memory Storage For Slim Smartphones & Tablets

Wednesday, November 14, 2012

Qualcomm, Globalfoundries +30% in Sales in 2012

Fabless chip manufacturer Qualcomm and foundry vendor Globalfoundries are each expected to move up IC Insights Inc.'s list of the top 20 chip vendors as ranked by sales in 2012 (see tables below.)

Both are benefitting from growth of mobile and tablet chip demands. Samsung is likely to lose sales due to Apple shifting production away from them. See more about foundaries ranking in 2011 and 2012.


Qualcomm, Globalfoundries gain in chip sales rankings

Dylan McGrath

11/8/2012 2:02 AM EST

Fabless giant, foundry forecast to climb to top 20 rankings ladder by growing sales by 30 percent in 2012. SAN FRANCISCO—Fabless chip giant Qualcomm Inc. and foundry vendor Globalfoundries Inc. are each expected to move up IC Insights Inc.'s list of the top 20 chip vendors as ranked by sales in 2012, according to the market research firm's latest forecast.

Both firms are expected to grow sales by at least 30 percent, according to IC Insights (Scottsdale, Ariz.). Qualcomm (San Diego) is on pace for 2012 revenue of more than $12.8 billion, fourth among all chip firms, up from seventh in 2011, according to the November Update to IC Insight's McClean Report. Meanwhile, Globalfoundries (Milpitas, Calif.) is on pace to move to No. 15 this year from No. 21 last year, with projected sales of $4.56 billion, according to the report.  
Additional information

Tuesday, November 13, 2012

FinFET Layout Design Rules and Variability

It is not simple to design circuits with FinFET transistors. Layout, 3D dimensions, and shape considerations are described in the article below. Some additional information about Intel's 22nm 3D Tri-Gate FinFETs Transistors.


FinFET structure design and variability analysis enabled by TCAD

Victor Moroz, Synopsys Inc.

10/8/2012 10:14 AM EDT

The introduction by Intel of FinFET transistors at the 22nm mode culminates many years of research and development of a replacement transistor to the immensely successful planar MOSFET whose progressive miniaturization is largely responsible for the electronics revolution. The need for a successor to the planar MOSFET had long ago been identified. Starting with the 90nm process node, improved transistor performance was achieved with the introduction of stress into the transistor channel in a way that boosts the speed of the electrons and holes traveling within it. However, controlling the transistor leakage in the off-state became progressively more difficult. Keeping the electrons and holes under the electrostatic control of the gate electrode is key to controlling leakage current, but a number of so-called short channel effects undermine the gate control. The introduction of high-k dielectrics as the gate insulator at the 45nm process node effectively extended the life of the planar MOSFET for another two process nodes, but by the 22nm process node the planar MOSFET could hardly offer an attractive balance of performance and leakage.

Intel’s FinFETs thus mark the first fundamental change in transistor architecture since the time when the MOSFET replaced the bipolar transistor as the transistor of choice for logic applications. Its performance improvements over the preceding process node (see table) are a clear indication of the promise this technology holds. Although the manufacturing of FinFETs is more complex than manufacturing of its planar predecessor, Intel’s introduction is a testament to the inevitability of these devices....   More at FinFET Layout Design and Variability

Monday, November 12, 2012

IEDM 2012 Preview: 20nm and Smaller

Some of the key issues in the upcoming IDEM 2012 are discussed in "Intel, rivals gird for IC manufacturing showdown" and in "IEDM preview: 20nm and below" .

"There have been three primary drivers in the semiconductor industry for the last four decades: Area, power/performance and cost. The well-known push to cram more functionality onto a single chip through continued scaling -- or into a single package through 3D integration and other advanced packaging techniques -- has been well documented. Today, with the exception of Intel, the industry's leading edge devices in high volume manufacturing have critical dimensions of 28nm. Intel, racing ahead, introduced the 22nm IvyBridge chip in 2011 and has announced plans to have 14nm by the end of 2013. How long this kind of scaling can continue is the subject of some debate, with most recognizing the EUV lithography will be required at some point, most likely for the 10nm generation (Intel has said it doesn't need it for 14nm).

It's clear, though, that continued scaling is running out of steam..."   Ron

Monday, November 5, 2012

Inside Microsoft Surface and Amazon Kindle Fire HD

"One big winner with the Surface appears to be Samsung. With one key exception —building the main processor chips —Samsung has been pushed out of Apple's iPad and iPhone products. For the Surface, Samsung supplied the display, the memory chips and the battery, amounting to about $137, or about half of the $271 bill-of-materials (BOM) cost."


Two More Teardowns Look Inside Microsoft Surface and Amazon Kindle Fire HD
Arik Hesseldahl  November 6

You have to credit the folks over at research firm IHS, because, apparently, they’ve pulling a little bit of overtime. Along with the teardown of Apple’s iPad mini, the results of which they sent to AllThingsD yesterday, they also included their first looks inside Microsoft’s Surface and Amazon’s seven-inch Kindle Fire HD.

Let’s get to the Surface first. (That’s a picture of it taken apart, at right.) With a base price of $499 for a 32 gigabyte Surface without the Touch Cover accessory, IHS estimates that the cost of components used to build it amount to $271 for a starter 32GB model, without the cover. The main components include a Tegra 3 processor chip from Nvidia, and a display and memory chips from Samsung. (Of course, Microsoft is probably buying memory chips from more than one vendor.)

Analyst Andrew Rassweiler, who led the IHS teardown team, said that Microsoft is using the relatively low entry price as a base, in hope of enticing consumers to buy higher-end models with the Touch Cover and higher memory capacity. The Touch Cover, which my colleague Walt Mossberg liked in his review of the Surface, costs $120 when purchased separately, and is bundled with the higher-end models.

Rassweiler estimates the cost of the parts used to build the Touch Cover at about $16, making it appear to be pretty profitable. It contains chips from Atmel and Freescale Semiconductor, he says. “It’s a compelling accessory for users to have, and a great example of a way in which manufacturers get consumers interested with a base price, and hope they’ll impulsively opt for extra features that make more profit,” he told me. Accessories always have higher profit margins than the devices they are intended to be sold with, Rassweiler says, and protective cases for phones and tablets always tend to sell well.

One big winner with the Surface appears to be Samsung. With one key exception — building the main processor chips — Samsung has been pushed out of Apple’s iPad and iPhone products. For the Surface, Samsung supplied the display, the memory chips and the battery, amounting to about $137, or about half of the $271 bill-of-materials (BOM) cost.

Now, on to the Kindle Fire HD. (Seen in its exploded view at right; click to make bigger.) Recall that the last Kindle Fire to get the teardown treatment came in with a cost estimate of $202 (later revised down to about $187) against a retail price of $199, meaning that Amazon was close or near to losing money on the hardware, and was hoping to make it back on the sale of content from its digital store, and even on sales of physical goods from its retail store. One estimate earlier this year suggested that Amazon makes more than $100 off each Kindle Fire. It’s probably pretty close to breakeven, if slightly profitable this time around, Rassweiler told me. Amazon CEO Jeff Bezos has said the devices are sold at cost.

Like the old one, the new Kindle Fire HD sells for a starting price of $199, and carries a combined cost of components of $165, according to IHS estimates. Key suppliers are LG Display, which made the screen; Texas Instruments, which repeated its role as the supplier of the main processing chip, plus power and video chips; and Samsung, which provided the memory.

Thursday, November 1, 2012

Intel's 14nm Process and Manufacturing Roadmap

With foundaries venturing into the FinFET devices it is interesting to see Intel's direction.

The article below with Mark Bohr, senior fellow at Intel, review the road map pertaining to a wide range of manufacturing and design issues. Some of the key points in the article are:

* Intel is sticking with bulk CMOS instead of SOI.

* FinFET transitors are scalable to 14nm process.

* "3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you’re trying to serve. For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution"

Additional information about Intel's 22nm at Tutorial: Intel 22nm 3D Tri-Gate FinFETs Transistors and at Intel’s 22-nm Tri-gate Transistors Exposed


Deep Inside Intel
By Ed Sperling

Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends.

SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel?

Bohr: For a process module as critical as lithography, Intel always has more than one option we pursue. In this era, the options are either EUV or 193nm immersion with multi-patterning.

SMD: How about directed self-assembly?

Bohr: That’s not a universally usable approach. You still need to define some layers with direct patterning, not a self-assembly technique. That’s a niche direction that will not replace these mainstream lithography techniques, but there may be some layers where it can complement the normal patterning techniques.

SMD: What’s your opinion about the future of the foundry business?

Bohr: The traditional foundry model is running into problems. In order to survive, the foundries will have to become more like an integrated device manufacturer. Even some of the chief spokespeople for the foundries have said something similar. The foundry model worked well when traditional scaling was being followed and everybody knew where we were headed. In this era, where you continually have to invent new materials and new structures, it’s a lot tougher being a separate foundry and maskless design house. Being an IDM, we have design and process development under one roof. That’s really a significant advantage.

SMD: Can even Intel afford to be an independent IDM? The cost of building state-of-the-art fabs at future nodes is astronomical.

Bohr: Yes. We have the volume and the products that can fill multiple fabs.

SMD: But you’ve also opened up your fabs to at least a couple customers. Are you planning on extending that? ,

Bohr: Our motivation is that we know we have great process technology, and partnering with other strategic companies can be a win-win situation. We can sell our technology and make more money off what we’ve developed, and they can have some very compelling products. It’s not Intel’s goal to be a general-purpose foundry, but we will be partnering where it makes strategic sense.

SMD: Is Intel sticking to bulk CMOS or will move to new materials such as fully depleted SOI?

Bohr: We see more advantages in bulk than SOI. I won’t say SOI won’t be in the future. There may be some device structure that is better done in SOI than bulk. But I don’t see than happening right now. When we first announced that we were making TriGate or finFET devices at 22nm, we said we’re making these devices on SOI, as well. But we think there are cost advantages to doing TriGate on bulk rather than SOI. That’s our plan for the foreseeable future.

SMD: What comes after the current finFET?

Bohr: The finFET is scalable to 14nm.

SMD: But if you’re at 22nm, 14nm isn’t very far away, so you’ve got to be working on the next step.

Bohr: For Intel, you’re right. For other companies, it’s many years away. For 10nm, which is where I’m spending most of my time these days, I know we have a solution. I can’t elaborate at this point.

SMD: At 10nm aren’t you running into quantum effects?

Bohr: Everything gets different and tougher, but the problems are solvable—at least at that generation.

SMD: How far ahead can you see?

Bohr: I know we can get to 10nm. Beyond that, our research group is working on solutions for 7nm and 5nm. I have confidence we’ll have solutions for those. But by the time we’re down to 5nm we’ll be looking at non-familiar devices and device structures. That’s what we’ll have to do to get down to that level.

SMD: Where do stacked die fit into your roadmap?

Bohr: 3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you’re trying to serve. For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution.

SMD: Along those lines, does Intel see the smart phone and small mobile device market as a key direction?

Bohr: Intel is very serious about getting into the smart phone and tablet markets. We are a very different company from what we were five or six years ago. We are developing process technologies, but also products, that span a much wider range of performance and power than anywhere in our history. We’re not just after the high-performance desktop. We’re developing products that support 100-watt server chips down to sub-1 watt smart phone chips.

SMD: There are a number of interesting techniques Intel is working with, such as near-threshold computing. How will power management start changing inside these chips?

Bohr: When you’re talking about developing a smart phone chip that is ultra low power that also provides improved performance features that the market expects, you have to pull every trick out of the bag. You need great transistor technology, great package technology, great CPU architectures, the ability to turn off parts of the chip when you don’t need them so you’re saving power, the software links with the chip design so the software knows when to throttle power down. You need transistors, CPU architecture and software to be effective in that space.

SMD: How many cores will be required in the future?

Bohr: It depends on the market. In the server market, the more cores you can pack on the better. But in desktops, laptops and smart phones, there’s probably a limit to how many cores are practical. It’s not one. It’s probably several.

SMD: But less than eight?

Bohr: Yes, probably less than eight. But when you talk about the number of cores and computing engines, it depends on whether you’re dealing with traditional computing tasks where four cores are better than two cores. If you’re talking about execution engines in a graphics processor, clearly you want more cores.

SMD: What does this do for Intel’s platform strategy, particularly as you go after many markets with very specific needs?

Bohr: Even for Intel there are probably an optimal number of chip designs. It’s not like in the past where we tried to make one size fit all or have one chip serve multiple markets. But on the other hand, trying to design and manufacture dozens of very different designs in a generation is also impractical. There’s an optimal number of designs, although I don’t know what that number is, that can best meet the market requirements. You want to make as few iterations between the different designs as you can or re-use the cores or some of the circuit blocks between the different chips so you’re not completely redesigning it.

SMD: Are there other materials being considered for transistors?

Bohr: Our research group has been publishing papers about using 3-5 materials for the channels. You deposit indium phosphide or gallium arsenide layer on top of silicon to make a transistor on the surface. It’s still a silicon wafer, but you’re looking at depositing more exotic materials. That’s new and different and it may happen, but it’s not yet fully resolved how good that approach may be.

SMD: Has the priority for what you’re designing into a chip changed? Is it still all about performance, or has power overtaken that?

Bohr: Ten or 15 years ago, performance was the main goal in developing a new process technology. That really has gone away as the No. 1 priority. We still strive to provide a performance boost with each new technology, but there’s much more emphasis on improving power or efficiency on each new generation. We do that by reducing active power for the work a chip does. That’s a much more important goal for us today. Part of the reason is that the market has shifted from desktop applications to more mobile products. The first transition was from desktops to laptops. Now the move is to put things into smart phones. Today’s consumer wants computing power he can hold in his hand in the form factor of a smart phone and a tiny battery. He wants the performance he had on his laptop only three or four years ago. That’s what we shoot for.

SMD: That shifts the biggest challenge to the architecture, right?

Bohr: Yes. Whether it’s low-power, low-leakage transistors or a more efficient core architecture—or linking that with more efficient software.

SMD: What becomes the next big bottleneck?

Bohr: We have lots of challenges. Lithography is the key challenge in making transistors smaller. Whether EUV will happen on time or we have to extend immersion using multiple patterning. But when you make transistors smaller they don’t become less leaky. In fact, the opposite is true. You have to continually invent new structures and materials to allow feature-size scaling, which is critical for active power reduction and for cost.

SMD: But wires don’t scale well. How do you deal with that?

Bohr: RC delay gets worse as you scale, compared with transistors, which tend to get faster as you scale down. The industry has had 20-plus years of struggling with that problem. One way we’ve addressed that is that we’re no longer striving for very high operating frequency, especially in the phone market where 2 or 2.5GHz would probably be sufficient. That’s one advantage. The other advantage is that the average size of the chips is smaller in these laptop and cell phone applications so you don’t have interconnects traveling a long distance across a large chip. Instead, it’s a more compact chip so the signals don’t have to go as far. But even with those chips, we still have a challenge of performance from the interconnect. We have to be clever about what pitches we choose. Some of the lower layers are dense pitch, where density is important. Some of the upper layers are coarser pitch, where performance is important. We’re also continuing to drive down interconnect capacitance by employing lower-k dielectrics.

SMD: Is the interconnect becoming more problematic?

Bohr: If you talk to a designer 10 years ago you would have heard the same thing. Maybe now they’re saying, ‘This time we’re really serious.’

SMD: How about new interconnect technology?

Bohr: It’s hard to replace copper and low-k other than by making lower k. But at least in the low-power cell phone market, stacking chips does help to minimize some of the interconnect issues, particularly between the logic and the memory chips.

SMD: You’re referring to through-silicon vias?

Bohr: Yes.

SMD: So if Intel is planning to get into that market, the company is experimenting with that technology right now?

Bohr: Yes, and we’ve been public about exploring TSV and 3D technology for a couple years. Although there are some challenging technology aspects, the real issue is cost. Doing TSVs and stacking chips—especially these custom Wide I/O chips—is expensive. So this might be a better engineering solution in terms of density, performance and power, but will the market bear the added cost? Not all markets will bear the higher cost.