Showing posts with label EUV. Show all posts
Showing posts with label EUV. Show all posts

Thursday, December 11, 2014

Semiconductor Manufacturing 2015 Demand

Key new drivers for new semiconductor fabrication tools is advancing FinFETs 20nm to 16nm/14nm with reasonable yield, and the pace of implementation of 3D NAND. 

Ramp up of 3D flash manufacturing tools will really happen only in 2016 due to length of the development cycle.


In lithography, multi-patterning will continue to be used while EUV continue to faces difficulties. More details are below.


Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/


Fab Tool Biz Faces Challenges In 2015

After a slight downturn in 2013, the semiconductor equipment industry rebounded and experienced a solid upturn in 2014. The recovery was primarily driven by tool spending in the foundry and DRAM [KC]sectors.
Another big and ongoing story continued to unfold in 2014. In late 2013, Applied Materials announced a definitive agreement to acquire Tokyo Electron Ltd. (TEL) for $9.3 billion. The deal was supposed to close in the second half of 2014. But now, the completion of the deal has been pushed out into 2015 amid a host of complicated regulatory issues.
In fact, the fate of the Applied-TEL deal is just one of the many burning issues for the industry in 2015. The other issues are also clear:
• Will IC-equipment vendors see an upturn or a downturn in 2015?
• What are the drivers?
• Will 450mm fabs, EUV [] and 2.5D [KC]/3D IC [KC] stacked die really happen?
• Will the equipment industry continue to see more acquisition activity in 2015?
The industry continues to consolidate and for good reason. At each node, there are simply fewer customers to serve in a maturing market. “More industry consolidation is needed in several areas, notably in process control and in the components/consumables market, where companies like MKS Instruments, Entegris and others participate,” said Patrick Ho, an analyst at Stifel Nicolaus. “So, will we see (acquisition activity) in 2015? There is a greater likelihood that the smaller players may combine with one another, versus any of the large players taking out the small players. My rationale: the big players are either busy, such as Applied and TEL, or content in their current positions for now. Longer term, we still need one more big deal to occur to further consolidate the space.”
Bold predictions
It’s difficult to predict the future, but there are signs that the Applied-TEL deal will get completed in 2015. So far, the deal has been approved by regulatory bodies in some countries, but not in others. “The deal gets done at some point,” Ho said. “Any deal of this size and scope, particularly when you’re dealing with a relatively consolidated customer base, will likely garner more scrutiny and even some pushbacks from customers. But like many other large deals, I believe ultimately it gets done with perhaps a few contingencies added on to the final deal.”
Another lingering issue is the IC-equipment forecast for 2015. There are mixed signals in the market. Economic growth remains sluggish in many countries. The worldwide geopolitical landscape is troubling. And in the electronics market, the two main catalysts for growth—smartphones and tablets—are showing signs of a slowdown.
As a result, the outlook is cloudy for tool vendors. In fact, citing the slowdown in mobile products and other factors, some are already lowering their forecasts for 2015. In its latest forecast, Gartner projected that semiconductor capital spending and the wafer fab equipment (WFE) market would grow by 11.4% and 17.1%, respectively, in 2014.
For 2015, Gartner currently predicts that semiconductor capital spending and WFE will grow by 8.8% and 11.1%, respectively. “At the moment, those numbers will probably come down a bit, as 2015 does not appear as robust as it did three months ago,” said Dean Freeman, an analyst with Gartner. “WFE for 2015 will be in the 5% to 10% range and CapEx will be closer to 5%. Much of this is dependent upon how much Samsung spends in Q4.”
Many other analysts have a similar forecast for 2015. But on the down side, the ATE market faces a possible downturn in 2015.
Drivers—DRAM, finFETs and NAND
Looking beyond the numbers, tool vendors are in the midst of the most challenging period in the industry’s history. Chipmakers are making a major transition from planar structures to various 3D-like architectures, such as 3D NAND, finFETs [KC] and stacked die.
Toolmakers, in turn, must develop new and advanced systems to meet customer requirements. But the cost to develop new tools is soaring out of control. And yet, there are fewer leading-edge customers at each node.
On the other hand, the shift towards new chip architectures are becoming the “inflection points”—or engines for growth–in the equipment industry, said Doug Bettinger, executive vice president and chief financial officer at Lam Research [], at a recent conference. “(The inflection points include) the move towards multi-patterning. That’s an enormous driver of growth,” Bettinger said. “It’s also the move to finFET from planar. It’s planar to 3D NAND, as well as the move to 3D packaging.”
In 2015, the big driver for fab tool orders will likely reside in the foundry segment, where GlobalFoundries [], Samsung and TSMC [] are making a transition from planar transistors at 20nm to finFETs at 16nm/14nm. Intel Corp. []is already ramping up its second-generation finFETs at 14nm.
For the foundry segment alone, WFE is expected to grow 5% to 10% in 2015, according to Stifel Nicolaus’ Ho. But tool orders for the finFET ramps are also somewhat dependent on one major factor—yield. The foundries, including Intel, are struggling with finFET yields. “With finFET, it will be a question of the magnitude of spending related to yields,” Ho said.
For DRAM, WFE is expected to grow 10% to 15% in 2015. And in NAND, WFE is projected to grow 5% to 10%, according to Stifel Nicolaus. In fact, the DRAM [KC] market remains strong. There could be a shortage of 2D NAND capacity in 2015. But with the exception of Samsung, vendors continue to push out their 3D NAND ramps.
“The timing of 3D NAND has been pushed out due to yields and demand, but the NAND flash industry will eventually transition to this technology,” Ho said. “The cost basis for planar NAND is still more attractive, so I believe the players will try and take advantage of this for two more nodes.”
Others also see a mixed picture in 2015. “In NAND, 3D spending is expected to be broader and larger, but it still lags planar spending until 2016. However, our customers are seeing diminishing gains from planar and (the) 3D adoption is inevitable. DRAM supply is expected to remain tight with strong potential for capacity additions,” said Gigi Lai, senior director of strategic marketing at Applied Materials. “Overall, we expect wafer fab equipment spending will be higher (in 2015), driven by the foundry finFET battle, broader investments in 3D NAND, and increasing DRAM spending.”
450mm and EUV
It’s safe to say that 450mm will not be a factor in 2015. In fact, the industry has put 450mm technology on hold for the foreseeable future. For now, 450mm is too expensive and the benefits are marginal.
But in 2015, the industry will keep a close eye on ASML’s ongoing efforts to put extreme ultraviolet (EUV) lithography into production. “If you look at the (recent) eBeam Initiative [] survey, it indicates that there is a little bit of an increase in the skepticism in EUV,” said Aki Fujimura, chairman and chief executive of D2S. “The survey echoes the statements from many in the industry: ‘We still want (EUV) to happen.’ But publicly, everyone is saying: ‘I don’t know if we can count on it. So we better have backup plans in place.’ “
Barring a major breakthrough in EUV, chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm. “It’s not the question whether you can do (multiple patterning). Technically, it is possible. The question is if it’s economically viable. Certainly, the economic viability answer is very different, depending on who you are,” Fujimura said.
Backend blues
For years, meanwhile, the industry has been talking about the development of 2.5D and 3D chips using through-silicon vias (TSVs). So far, though, 2.5D/3D technology is taking longer than expected amid a number of cost and technical challenges. “We have stuff in production today. But again, these are high-performance applications,” said Jan Vardaman, president of TechSearch International. “Besides Xilinx, there are other people that are developing products using an interposer that should come out in 2015.”
So when will 2.5D/3D stacked die hit the mainstream? “These are new architectures,” Vardaman said. “New architectures take a long time to develop and you have to sort them out carefully.”
The ATE industry, meanwhile, is expected to grow by 20% in 2014. That was driven by booming demand for test in the mobile-based application processor space. Not long ago, Pacific Crest Securities projected that the ATE market would grow by 10% in 2015. But the firm recently lowered its forecast and now projects a 2% decline for ATE in 2015.

Wednesday, November 12, 2014

Samsung 3D Process Pioneers Next Gen Semiconductor Devices

Samsung is leading the semiconductor industry with a two year leads in development of 3D NAND (see the article below).


The basic 3D process could be applied to other technologies beside flash such as DRAM memory or logic. It enable increasing the number of the transistors on each dies without the need to shrink the design rules below 20nm.

It is a key advantages since you do not need to develop the very difficult EUV photolitography.

More about 3D NAND in August 2013 blog - Samsung’s 1Tb SSD: 3D Vertical NAND

It make sense for Samsung to apply 3D Flash first to enterprise SSD, where the growth rate is +40%.

See also Applied Materials development work on advance patterning  - Applied Materials Develops Advanced Patterning Solution for Memory Devices


Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/




samsung_hwaseong_2optimized.jpg

An aerial view of Samsung's Hwaseong plant.
10 NOVEMBER 2014
Samsung Electronics is working to strengthen its position in the SSD market by increasing the profitability of its semiconductor memory business.
According to industry sources on Nov. 9, Samsung established a strategy to choose 3-bit V-NAND-based SSD as a new growth engine of its semiconductor memory business.
Since the productivity of 3-bit V-NAND is twice as high as 10 nm class planar NAND flash, the V-NAND is superior in price competitiveness, data processing speed, durability, and power efficiency. Thus, if the 3-bit V-NAND is featured in SSDs, it will increase the performance and price competitiveness of SSDs.
After its success in having a system to mass produce 3-bit V-NAND at the company's semiconductor plant in Hwaseong City near Seoul early last month, the Korean chip maker started to prepare for mass production at its 3D V-NAND production facility in Xian, China.
Considering that it normally takes six months to expand a mass production system to other plants, the industry anticipates that 3-bit V-NAND will be mass produced starting in May or April of next year.
The semiconductor plant in Hwaseong City produces mainly planar NAND flash for mobile devices, and thus it manufactures less than 100,000 V-NAND 300 mm wafers per month.
In contrast, the 3D V-NAND production facility in Xian, which commenced full operations in May, manufactures 300,000 to 400,000 sheets each month. However, the facility is considered to have capacity to produce more than 700,000 sheets.
Samsung aims to strengthen its dominant position in the market by increasing its share in the SSD market through the use of 3-bit V-NAND in SSDs.
The Korean company revealed that it will feature 3-bit V-NAND in SSDs starting next year at a conference call, following its announcement of results for the third quarter at the end of October.
Samsung's decision can be interpreted to mean that it intends to widen the gap with its rival companies in the global market by featuring 3-bit V-NAND in SSDs used in a data center environment and SSDs for PCs.
Market research firm IHS Technology recently reported that the world's largest memory chip maker will record US$3.277 billion in sales from SSDs in 2014, a 60 percent year-on-year gain. Its market share is expected to increase from 26 percent to 29 percent this year, which will put the firm in the top spot, followed by Sandisk with a 19 percent share, Intel (18 percent), Toshiba (9 percent), and Micron Technology (8 percent).
Currently, Samsung is the only company in the world that produces 3D V-NAND flash memory chips. The gap with rival companies in technology is generally acknowledged to be more than two years.
- See more at: http://www.businesskorea.co.kr/article/7217/focusing-ssds-samsung-mass-produce-3-bit-3d-nand-flash-ssd#sthash.vOPJFbm8.dpuf

Thursday, April 26, 2012

Intel: "Fabless model collapsing". Is it correct?


Intel’s top process technology exec says the foundry model is collapsing.  A good manufacturing process is only one of the factors that leads to success in product and circuit strategies. Intel had been leading in manufacturing with the HKMG process since the 45nm process.

However, they were not able to use their manufacturing clout to lead in new areas such as the mobile phone microprocessor market.

TSMC, GlobalFoundries, and UMC will have to work closer with the fabless companies sharing resources and cost to address these challenges.


Ron Maltiel

Tuesday, March 27, 2012

While FinFET Charging Ahead, Other 20nm challenges

While the industry is following Intel's lead with FinFET transistors, there are several additional major problems in continuing semiconductors technology scaling. Some key problems are discussed below.

More on 22nm challenges.

Ron Maltiel



Top Five Design and Manufacturing Challenges at 20nm

http://semimd.com/blog/2012/03/21/top-five-design-and-manufacturing-challenges-at-20nm/
By Mark LaPedus

The hottest topic in the leading-edge silicon foundry world centers around the shift from planar transistors to finFET structures at the 14nm process node.

GlobalFoundries, Samsung, TSMC and UMC are racing each other to develop finFETs at the 14nm node. But the industry is getting ahead of itself, as experts warn there are still enormous IC design and manufacturing challenges at the 20nm process node. The foundries will continue to use planar transistor structures at 28nm and 20nm, with plans to move to finFETs at 14nm.

Some but not all foundries are still struggling to ramp up their processes based on high-k/metal-gate schemes at the 28nm node. While vendors are seeing various challenges at 28nm, the 20nm node is expected to be even more daunting. “It’s a brave new world at 20nm,” said Tom Beckley, senior vice president of research and development for custom IC and signoff for the Silicon Realization Group at Cadence Design Systems Inc.

At 20nm, there are also economic factors involved, namely fab, process and design costs. And there are also technology challenges, such as the advent of double patterning, severe layout-dependent effects, as well as the introduction of a new and third layer of local interconnect in the design.

That layer — or the so-called middle of the line (MOL) — will likely become “disruptive” in the IC flow, said Luigi Capodieci, director of DFM/CAD and R&D Fellow at silicon foundry vendor GlobalFoundries Inc. Capodieci and Beckley were among the keynoters at the 13th International Symposium on Quality Electronic Design (ISQED) in Santa Clara, Calif. on Tuesday (March 20).

There are a multitude of design and manufacturing challenges at the 20nm node. Based on the keynote presentations from the two design/foundry experts at ISQED, here are five of the bigger design/manufacturing challenges — and trends — at 20nm:


1. The economics factors favor a select few

Chip scaling enables smaller devices at lower costs, but there are also some major ramifications: Fewer and fewer vendors can participate as the industry marches down to the smaller nodes. Only the players with deep pockets can afford to play at 20nm. It’s simply becoming too expensive for most to play at the bleeding-edge of IC design and manufacturing.

The foundries are seeing a clear trend at the leading-edge. “The number of tape outs is decreasing, but the volumes are much higher,” said GlobalFoundries’ Capodieci during his keynote at ISQED.

Citing International Business Strategies Inc. (IBS), a research firm, Cadence’s Beckley said at the 32/28nm nodes, a fab runs $3 billion, process R&D is $1.2 billion, IC design costs ranges from $50 million to $90 million, and mask costs are from $2 million to $3 million.

Citing the same research firm, he said at the 22/20nm nodes, a fab will cost $4 billion to $7 billion, process R&D runs from $2.1 billion to $3 billion, design costs run from between $120 million to $500 million, and mask costs are from $5 million to $8 million.

From his own data, he said EDA tool costs in total run from $800 million to $1.2 billion for the 22/20nm nodes, compared to $400 million to $500 million for 32nm/28nm. Another troubling trend is verification. “Verification times are exploding,” he added.

The solution to the problem? In the past, circuit designers and layout engineers lived in separate silos. The two groups will need to collaborate in order to deal with the complexities involved at 20nm and beyond, Beckley said.


2. Double patterning has (unfortunately) entered the spotlight

The IC industry has pushed 193nm wavelength lithography much further than previously thought. Amazingly, on the logic front, the IC industry is using today’s 193nm immersion scanners based on signal-exposure techniques at the 32nm/28nm nodes.

But due to the delays with the various next-generation lithography (NGL) candidates — namely extreme ultraviolet (EUV) — the industry must embrace 193nm lithography and multi-patterning at 20nm and perhaps beyond. Today, Toshiba Corp. and SanDisk Corp. are making 19nm NAND devices using 193nm immersion scanners — and with the help of a resolution enhancement technique (RET) called self-aligned double patterning. Meanwhile, at 22nm, Intel Corp. is using 193nm immersion — with the help of some form of double-patterning technique.

Double pattering involves separate exposures of the same layer using two photomasks, which, in turn, adds complexity and cost in chip manufacturing.

“At 20nm, the foundries will require double-patterning,” said Beckley during his ISQED keynote, but that “brings coloring” into the mix. In double-patterning, the layout patterns are split and decomposed into two masks. The polygons or features are assigned opposite colors.

The question is whether the coloring is managed by the designer or foundry. That process should not be managed by the foundry, he said. “Coloring must be managed within the design methodology and saved as an integral part of the IP,” he said.

At 20nm, the foundries will likely embrace a double-pattering technique that involves “litho-etch-litho-etch (LELE),” said GlobalFoundries’ Capodieci. LELE poses some challenges in terms of the composition/decomposition steps and overlay. “Overlay can cause local line width variations or local space CD variations depending on the process scheme, which translates into electrical degradation,” he said.

At 20nm, GlobalFoundries and its EDA partners are working on adding “double-patterning-aware” technologies to solve many of the issues. To get around many of these issues, the IC industry is banking on extreme ultraviolet (EUV) lithography. But EUV is late and is a question mark for 14nm. The problem continues to be the power source and throughput.

EUV remains the lithography technology for “tomorrow,” said Capodieci. “Tomorrow’s lithography is still happening tomorrow.”

3. New routing layers

At 28nm and above, the manufacturing flow consists of two parts: front-end-of-the-line (FEOL) and backend-of –the-line (BEOL). The FEOL involves the formation of the transistors and logic, while BEOL handles the vias, interconnects and other structures.

At 20nm, the foundries are now talking about a third layer of interconnect. That layer — or MOL — will become another challenge in the manufacturing flow, Capodieci said.

As a result, the industry will require “new methodologies” to address the new routing layer, said Cadence’s Beckley.


4. Severe layout-dependent effects
Beckley said severe layout-dependent effects are expected at all advanced nodes. Shallow trench isolation (STI) and well proximity effect (WPE) are two types of layout-dependent effects. So it is important that vendors get involved “early in the design stage to handle the parasitics,” he said.


5. More DFM to the rescue

Is Moore’s Law slowing down? “The answer is that it is not for the memory and processor IDMs, but definitely for the foundries,” said G. Dan Hutcheson, president of VLSI Research Inc. “The alarming thing about it is that the ability of foundries to convert their process development and tool investments into revenues has been steadily declining since 130nm. The importance of 130nm is that’s when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then.”




Is foundry model falling apart? (Source: VLSI)

”What’s more scary about the chart is that the decline is predictable, forming a steady downward trend,” said Hutcheson. ”Meanwhile, the fabless companies at the leading edge, such as Nvidia and Qualcomm are visibly concerned about their foundries’ ability to keep up with Moore’s Law. To stay in the game they need a steady decline in cost-per-transistor. If anything, this chart certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”

The solution? EDA houses, foundries and fabless chip makers must ”partner more closely,” he said. ”But this comes at a time when the foundries have become more mistrustful, communicating less about upcoming processes. One thing is clear: If these issues don’t get resolved, there will be a major restructuring of the industry.”

Amid these alarming trends, there is also pressure among chip makers to develop more robust designs — and ensure they can be manufactured in a timely fashion. To meet these challenges, IC vendors have recently embraced — and put more emphasis — on DFM. As part of the DFM equation, chips yields — and the yield enhancement process — have become even more critical.

Within that technology, GlobalFoundries has worked with Mentor to develop a flow to boost yields. In another major step to solve the problem, Cadence and GlobalFoundries recently teamed up to reduce the turnaround times for DFM signoff at 28nm. It’s likely that this technology will be migrated to 20nm.

Using Cadence’s “in-design” DFM tools, GlobalFoundries calls the technology DRC+. The core of the DRC+ flow is two-dimensional shape-based pattern matching, which offers speed improvements in error detection and fixing. This technology enables customers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.

In the DFM world, this is a step in the right direction. GlobalFoundries’ Capodieci said the technology is 10,000 times faster than simulations

Friday, March 23, 2012

Moore's Law Slowwwing

Below is another example of the end of Moore's law.
See also earlier post.

Ron Maltiel

Feature dimension reduction slowdown
http://www.eetimes.com/discussion/other/4238315/Feature-dimension-reduction-slowdown
Handel Jones ,  3/20/2012 12:32 AM EDT

The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase. The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase.

1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.

2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.

3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.







Figure 1- Cost per gate.

With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.

4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.

EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.

The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.

Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.

New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.

What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.

After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.

The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.

Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.

With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.

Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.



Saturday, June 13, 2009

Samsung- 5 nm is Not a Limit to Silicon Scaling

Speaking at IMEC's Technology Forum this week...Kinam Kim of Samsung Electronics asserted that he believes silicon scaling will continue far beyond the nanometer range....

Kinam Kim of Samsung Electronics noted that some people in industry say the limit of scaling is ~5 nm, to which he said, "I do not agree." In fact, he said he believes that there are various possible paths to overcome obstacles of silicon scaling to continue to grow the silicon industry far beyond the nanometer range. Kim, executive vice president and general manager of Samsung's Semiconductor R&D Center and Samsung Fellow, presented at IMEC's Technology Forum in Brussels, Belgium, this week.

Kim said that despite the global economic recession and slowdown of semiconductor markets, most notably memory, several emerging drivers exist in healthcare, IT, automotive, aerospace and robotics, and will be strong engines for silicon growth in the future. Healthcare alone will become predictive, preventive and personalized, using such technologies as biogenics. Advanced robots will use a variety of sensors, combined with computing power, to perform any number of tasks. It will be the incumbent applications of the semiconductor industry, well-known applications in wireless computing and entertainment, which will feed into these emerging applications... Samsung is optimistic that EUV double patterning (NA=0.25, 0.32, then 0.6) will take patterning to several nanometers in 2014.. Additional details

Laura Peters, Editor-in-Chief -- Semiconductor International, 6/4/2009http://www.semiconductor.net/article/278328-Samsung_s_Kim_Claims_No_Limit_to_Scaling.php