Chipwork's teardown of the new Apple iPad 4 reveals a major redesign of the graphic processor (GPU). The much larger area dedicated to the GPU and wider interface of the DRAM improves the display and touch screen performance of the iPad 4. It probably also helps prolong battery life.
" The A6 is 94mm2 while the A6X is 123mm2 – a full 30% larger.So where did that extra area go? Well, firstly, it did not go to the CPU core. The A6X uses the identical CPU to the A6. Same size, same layout. This is not surprising given that the prior CPU used custom layout techniques, and therefore it would be a huge amount of work to redesign so soon. Much of the extra area has gone to the GPU cores which are up from 3 to 4. More notable is that each of these GPU cores is much larger.On the A6X each GPU core is 8.7mm2 while the A6 GPU cores are only 5.4mm2. The overall area occupied by the A6X GPU cores is more than double that of the A6!
So we see that of the 29 mm2 of new area on the A6X, a full 18.6 mm2 is the result of the increased quantity of graphics processing. Impressive!
Additionally, if you look closely at the GPU cores (which our high magnification scopes allow us to do), we can see they are actually split into sub-cores themselves. Each GPU core is sub-divided into 9 sub-cores (2 sets of 4 identical sub-cores plus a central core). This could be done to allow for more efficient parallel processing, or to allow for a higher maximum clock rate. In either case, these GPUs should result in some blazing graphics on your iPad.
Other items of note:
It looks like the A6X has double the SDRAM interface width of the A6 (again likely to allow for greater graphics processing power).
Other than the CPU, it appears all the other digital cores have new layouts. This chip is not just a minor tweak from the A6, a lot of work has gone into this.
Apple has reduced the number of core PLLs needed from 9 on the A6 to 8 on the A6X. However they have moved them close to the middle of the chip which may allow for better control over clock skew across the chip.
Many of the analog and interface cores have been reused from the A6, however there are also some new interface blocks."
Additional information
Ron Maltiel
www.maltiel-consulting.com
Commentary on Semiconductor industry at the confluence of Process, Product, and Circuits design
Contact Info.
Semiconductor Information and Business News at http://maltiel-consulting.com/
mailto:ron@maltiel-consulting.com
Phone / Fax : (408) 446 - 3040
mailto:ron@maltiel-consulting.com
Phone / Fax : (408) 446 - 3040
Showing posts with label 45nm. Show all posts
Showing posts with label 45nm. Show all posts
Thursday, December 13, 2012
Tuesday, October 30, 2012
Apple's A6X Processor 32nm Process Advantages
Apple's latest iPad 4 processor comes with its latest processor: an A6X, which Apple says delivers twice the CPU and graphics performance as the A5X. See below some details about Apple's A6X processor.
"Apple moved from a 45nm process to a more power-efficient 32nm process. Instead of keeping performance the same and decreasing the iPad's thickness and weight, Apple instead chose to double its performance without sacrificing all-day battery life."
More about Apple's optimizing process and design at iPhone A6 Teardown Update
Ron
http://www.maltiel-consulting.com/
Deducing details about Apple's A6X processor
Apple promises double the CPU and graphics performance over the A5X, but how?
by Chris Foresman - Oct 23 2012, 3:25pm PDT
As usual, Apple didn't share many specifics about its new A6 "Extreme" (A6X) processor, which powers the fourth-generation iPad. However, by looking at Apple's claims that it's "twice as fast" as the A5X-powered third-gen iPad, it may be possible to deduce what's inside.
According to Apple, the A6X processor "delivers up to twice the CPU and graphics performance of the A5X chip." In other words, the dual-core CPU can process data twice as fast as the dual-core 1GHz, Cortex A9-based A5X. It can also churn through OpenGL triangles and textures at twice the rate of the PowerVR SGX543MP4 in the A5X. So how did Apple do that?
Looking at CPU power for the moment, we already know that Apple designed a custom ARM-based core for the A6. Running at 1.2GHz in the iPhone 5, two A6 cores run twice as fast as two 800MHz A5 cores in an iPhone 4S.
However, the A5X in the third-gen iPad was clocked at 1GHz. That means Apple is clocking the A6X higher yet. Given that architectural improvements account for some of the speed increase, Apple only had to clock the iPhone 5 at 150 percent to achieve double the compute performance of the iPhone 4S. With this in mind, we believe Apple is clocking the A6X's CPU cores at 1.5GHz.
Examining the GPU is slightly different. Apple already jammed four SGX543 GPU cores into the A5X in order to achieve performance parity with the two SGX543 GPU cores in the A5 chip that powers the iPad 2. The extra GPUs were needed just to keep up with the 2048×1532 pixel Retina display, so these did not offer any graphics performance improvement. However, Apple says that the A6X pumps pixels twice as fast.
Apple could be using a newer-generation PowerVR core, but that appears to be very unlikely. Only one announced processor is known to use a PowerVR Series6 design, and it won't even begin sampling until 2013. Given that Apple just released the A6 a month ago, we're confident Apple is still using the same SGX543 core.
Here's what we know about the PowerVR SGX543 core's performance: it scales almost linearly with the number of cores and clock speed. So to double the performance, Apple would either have to double the number of cores to eight or double the clock speed of each of the four cores. Apple says that the A6X has "quad-core graphics"—the same as the A5X—so Apple clearly boosted the clock speed. Since the GPUs in the A5X were clocked at 250MHz, we believe that Apple has clocked the SGX543 cores at 500MHz.
Given the significant boosts in clock frequency—150 percent for the CPU cores, and 200 percent for the GPU cores—you may be wondering how Apple can still promise a 10-hour battery life. After all, the iPad still has the exact same 42.5Whr battery, but the processor is twice as powerful. The power savings come from the same place as we saw in the iPhone—Apple moved from a 45nm process to a more power-efficient 32nm process. Instead of keeping performance the same and decreasing the iPad's thickness and weight, Apple instead chose to double its performance without sacrificing all-day battery life.
Of course, we won't know how accurate our educated guesses are until one of the new iPads can be thoroughly benched, and the A6X's architecture is analyzed by the likes of Chipworks. However, we feel confident suggesting Apple has mated two A6 ARM cores running at 1.5GHz with four PowerVR SGX543 cores running at 500MHz. Given the performance results we saw with the iPhone 5, we expect the updated iPad will remain at the top of the tablet performance heap for some time.
"Apple moved from a 45nm process to a more power-efficient 32nm process. Instead of keeping performance the same and decreasing the iPad's thickness and weight, Apple instead chose to double its performance without sacrificing all-day battery life."
More about Apple's optimizing process and design at iPhone A6 Teardown Update
Ron
http://www.maltiel-consulting.com/
Deducing details about Apple's A6X processor
Apple promises double the CPU and graphics performance over the A5X, but how?
by Chris Foresman - Oct 23 2012, 3:25pm PDT
As usual, Apple didn't share many specifics about its new A6 "Extreme" (A6X) processor, which powers the fourth-generation iPad. However, by looking at Apple's claims that it's "twice as fast" as the A5X-powered third-gen iPad, it may be possible to deduce what's inside.
According to Apple, the A6X processor "delivers up to twice the CPU and graphics performance of the A5X chip." In other words, the dual-core CPU can process data twice as fast as the dual-core 1GHz, Cortex A9-based A5X. It can also churn through OpenGL triangles and textures at twice the rate of the PowerVR SGX543MP4 in the A5X. So how did Apple do that?
Looking at CPU power for the moment, we already know that Apple designed a custom ARM-based core for the A6. Running at 1.2GHz in the iPhone 5, two A6 cores run twice as fast as two 800MHz A5 cores in an iPhone 4S.
However, the A5X in the third-gen iPad was clocked at 1GHz. That means Apple is clocking the A6X higher yet. Given that architectural improvements account for some of the speed increase, Apple only had to clock the iPhone 5 at 150 percent to achieve double the compute performance of the iPhone 4S. With this in mind, we believe Apple is clocking the A6X's CPU cores at 1.5GHz.
Examining the GPU is slightly different. Apple already jammed four SGX543 GPU cores into the A5X in order to achieve performance parity with the two SGX543 GPU cores in the A5 chip that powers the iPad 2. The extra GPUs were needed just to keep up with the 2048×1532 pixel Retina display, so these did not offer any graphics performance improvement. However, Apple says that the A6X pumps pixels twice as fast.
Apple could be using a newer-generation PowerVR core, but that appears to be very unlikely. Only one announced processor is known to use a PowerVR Series6 design, and it won't even begin sampling until 2013. Given that Apple just released the A6 a month ago, we're confident Apple is still using the same SGX543 core.
Here's what we know about the PowerVR SGX543 core's performance: it scales almost linearly with the number of cores and clock speed. So to double the performance, Apple would either have to double the number of cores to eight or double the clock speed of each of the four cores. Apple says that the A6X has "quad-core graphics"—the same as the A5X—so Apple clearly boosted the clock speed. Since the GPUs in the A5X were clocked at 250MHz, we believe that Apple has clocked the SGX543 cores at 500MHz.
Given the significant boosts in clock frequency—150 percent for the CPU cores, and 200 percent for the GPU cores—you may be wondering how Apple can still promise a 10-hour battery life. After all, the iPad still has the exact same 42.5Whr battery, but the processor is twice as powerful. The power savings come from the same place as we saw in the iPhone—Apple moved from a 45nm process to a more power-efficient 32nm process. Instead of keeping performance the same and decreasing the iPad's thickness and weight, Apple instead chose to double its performance without sacrificing all-day battery life.
Of course, we won't know how accurate our educated guesses are until one of the new iPads can be thoroughly benched, and the A6X's architecture is analyzed by the likes of Chipworks. However, we feel confident suggesting Apple has mated two A6 ARM cores running at 1.5GHz with four PowerVR SGX543 cores running at 500MHz. Given the performance results we saw with the iPhone 5, we expect the updated iPad will remain at the top of the tablet performance heap for some time.
Tuesday, May 1, 2012
US Fabs Losing Their Edge. Really?
It is true that "As chip plants get pricey, U.S. risks losing edge", as the article state.
However we should keep in mind that Apple has Samsung manufacture their A5 processor (that runs the iPad) at Samsung's Texas fab. Apple manufactures in Texas due to the need for a close interaction between Apple's R&D and the Fab development and manufacturing groups. Such eco systems of technologies are a very important part of the development, production, and product supply chain.
The US still has some good manufacturing fabs. Intel is a good example. Intel has been extending its lead in manufacturing since the HKMG 45nm process.
As the article mentions, the future of US semiconductors will be strengthened by the industry's joint development of 450mm wafer manufacturing. It is important for the USA to maintain their current position.
Friday, March 23, 2012
Moore's Law Slowwwing
Below is another example of the end of Moore's law.
See also earlier post.
Ron Maltiel
Feature dimension reduction slowdown
http://www.eetimes.com/discussion/other/4238315/Feature-dimension-reduction-slowdown
Handel Jones , 3/20/2012 12:32 AM EDT
The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase. The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase.
1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.
2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.
3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.
Figure 1- Cost per gate.
With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.
4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.
EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.
New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.
What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.
After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.
The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.
Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.
See also earlier post.
Ron Maltiel
Feature dimension reduction slowdown
http://www.eetimes.com/discussion/other/4238315/Feature-dimension-reduction-slowdown
Handel Jones , 3/20/2012 12:32 AM EDT
The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase. The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase.
1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.
2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.
3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.
Figure 1- Cost per gate.
With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.
4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.
EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.
New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.
What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.
After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.
The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.
Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.
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