Intel's 3D XPoint Bottlenecks

While Intel's 3D XPoint technology will improve the speed of the CPU communicating with the memory, it will uncover new bottlenecks. The overall system speed is always limited by the weakest link in the chain. 3D XPoint will improve the overall system speed (based on Intel's data). However, depending on specific system setups and the details of their operations, there will be new bottlenecks that will limit the improvement of this new technology.

We saw similar evolution when SSD technology was implemented with new bottlenecks popping up over the last +8 years ( SSD The Next Killer App in NAND Flash - Jim Elliott / Samsung ) .  For example, there are still a lot of issues with storing data in cache of an SSD system as the cache  memory gets filled. See - Why Solid-State Drives Slow Down As You Fill Them Up and How can SD cards be faster than SSDs?



Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Intel’s 3D XPoint fixes bottlenecks

November 5, 2015 by Nick Farrell.

Chipzilla and Micron have been working on 3D XPoint technology which they say will close the performance gap between memory, CPU, and networking.

Until now details of the project have been kept under wraps, but now it seems the pair are keen to talk about it. All Intel would say is that it promised about 1,000 times the performance of NAND flash, 1,000 times the endurance of NAND flash, and about 10 times the density of DRAM.

3D XPoint technology is a 3D stacked memory with high-speed interconnects that can be used like DRAM and like flash storage.

Intel CEO Brian Krzanich is now saying that Intel will sell the memory under the Optane brand, and The Next Platform.

Memory is a bottleneck forcing CPUs to wait. Krzanich Optane would speed things up so processors are no longer waiting for data to arrive from memory or storage, in this case flash drives.

Krzanich showed a pair of matching servers. One server had Intel’s P3700 NAND PCI Express SSD and the other was a prototype Optane SSD. The Optane SSD outperformed the P3700 by 4.4 times in IOPS with 6.4 times less latency.

He said that Intel would release Optane next year and will “transform how we think about data and memory and storage.” The company will also come out with Optane DIMMs later this year for early testers. These will combine the performance of DRAM with the capacity and cost of flash.

A two-socket server with Optane DIMMS will have a total of 6 TB of addressable memory, “virtually eliminating paging between memory and storage, taking performance truly to a whole new level.”

- See more at: http://www.techeye.net/chips/intels-3d-xpoint-fixes-bottlenecks#sthash.n79kXMNz.dpuf

Bottlenecks: DRAM & Moore's Law

In addition to Moore's law slowing there are bottlenecks between the memory device and the CPU. 

The article below discusses

" How long will it will it take to find a technology so fundamentally different and better from anything we have today that we can do away with the DRAM latency and power consumption bottleneck?

There is a need for -

"A new RAM technology that cut main memory accesses by an order of magnitude would be reason enough to reevaluate the entire balance of resources on a microprocessor. If accessing main memory was as fast as accessing the CPUs cache, you might not need cache on the CPU die or package at all — or at least, you wouldn't need anything beyond L1 and maybe a small L2."

More about Moore's Law bottleneck from March 2012 Moore's Law End? (Next semiconductors gen. cost $10 billion)

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Forget Moore’s law: Hot and slow DRAM is a major roadblock to exascale and beyond

• By Joel Hruska on July 14, 2014 at 11:10 am
• • 
    

DRAM is pretty amazing stuff. The basic structure of the RAM we still use today was invented more than forty years ago and, just like its CPU cousin, it has continually benefited from the huge improvements that have been made in fabrication technology and density improvements. Less than ten years ago, 2GB of RAM was considered plenty for a typical desktop system — today, a high-end smartphone offers the same amount of memory but at a fifth of the power consumption.

After decades of scaling, however, modern DRAM is starting to hit a brick wall. Much in the same way that the CPU gigahertz race ran out of steam, the high latency and power consumption of DRAM is one of the most significant bottlenecks in modern computing. As supercomputers move towards exascale, there are serious doubts about whether DRAM is actually up to the task, or whether a whole new memory technology is required. Clearly there are some profound challenges ahead — and there’s disagreement about how to meet them.

What’s really wrong with DRAM?

A few days ago, Vice ran an article that actually does a pretty good job of talking about potential advances in the memory market, but includes a graph I think is fundamentally misleading. That’s not to sling mud at Vice — do a quick Google search, and you’ll find this picture has plenty of company:

The point of this image is ostensibly to demonstrate how DRAM performance has grown at a much slower rate than CPU performance, thereby creating an unbridgeable gap between the two system. The problem is, this graph no longer properly illustrates CPU performance or the relationship between it and memory.  Moore’s law has stopped functioning at anything like its historic level for CPUs or DRAM, and “memory performance” is simply too vague to accurately describe the problem.

The first thing to understand is that modern systems have vastly improved the bandwidth-per-core ratio compared to where we sat 14 years ago. In 2000, a fast P3 or Athlon system had a 64-bit memory bus connected to an off-die memory controller clocked at 133MHz. Peak bandwidth was 1.06GB/s while CPU clocks were hitting 1GHz. Today, a modern processor from AMD or Intel is clocked between 3-4GHz, while modern RAM is running at 1066MHz (2133MHz effective for DDR3) — or around 10GB/sec peak. Meanwhile we’ve long since started adding multiple memory channels, brought the memory controller on die, and clocked it at full CPU speed as well.

The problem isn’t memory bandwidth — it’s memory latency and memory power consumption. As we’ve previously discussed, DDR4 actually moves the dial backwards as far as the former is concerned, while improving the latter only modestly. It now looks as though the first generation of DDR4 will have some profoundly terrible latency characteristics; Micron is selling DDR4-2133 timed at 15-15-15-50. For comparison, DDR3-2133 can be bought at 11-11-11-27 — and that’s not even highest-end premium RAM. This latency hit means DDR4 won’t actually match DDR3′s performance for quite some time, as shown here:

This is where the original graph does have a point — latency has only improved modestly over the years, and we’ll be using DDR4-3200 before we get back to DDR3-1600 latencies. That’s an obvious issue — but it’s actually not the problem that’s holding exascale back. The problem for exascale is that DRAM power consumption is currently much too high for an exascale system.

The current goal is to build an exascale supercomputer within a 20MW power envelope,sometime between 2018 and 2020. Exascale describes a system that has exaflops of processing power, and perhaps hundreds of petabytes of RAM (current systems max out at around 30 petaflops and only a couple of petabytes of RAM. If today’s best DDR3 were used for the first exascale systems, the DRAM alone would consume 54MW of power. Clearly massive improvements are needed. So how do we find them?

Reinvent the wheel — or iterate like crazy

There are two ways to attack this problem, and they both have their proponents. One method is to keep building on the existing approaches that have given us DDR4 and the Hybrid Memory Cube. It’s reasonably likely that we can squeeze a great deal of additional improvement out of the basic DRAM structure by stacking dies, further optimizing trace layouts, using through-silicon vias (TSVs), and adapting 3D designs. According to a recent research paper, this could cut the RAM power consumption of a 100-petabyte supercomputer from 52MW (assuming standard DDR3-1333) to well below 10MW depending on the precise details of the technology.

While 100PB  is just one tenth of the way to exascale, reducing the RAM’s power consumption by an order of magnitude is unquestionably on the right track.

The other, more profound challenge, is the idea of finding a complete DRAM replacement. You may have noticed that while we cover new approaches and alternatives to conventional storage technologies, virtually all the proposed methods address the shortcomings of NAND storage — not DRAM. There’s a good reason for that — DRAM has survived more than 40 years precisely because it’s been very, very hard to beat.

The argument for reinventing the wheel is anchored in concepts like memristors, MRAM,FeRAM, and a host of other potential next-generation technologies. Some of them have the potential to replace DRAM altogether, while others, like phase change memory, would be used as a further buffer between DRAM and NAND. The big-picture fact that Vice does get right is that discovering a new memory technology that was faster and lower power than DRAM really would change the fundamental nature of computing — over time.

It’s easy to forget that the trends we’re talking about today have literally been true for decades. 11 years ago, computer scientist David Patterson presented a paper entitledLatency Lags Bandwidth, in which he measured the improvements in bandwidth against data accesses across CPUs, DRAM, LAN, and hard drives (SSDs weren’t a thing at that time). What he found is summarized below:

In every case — and in a remarkably consistent fashion — latency improved by 20-30% in the same time that it took bandwidth to double. This problem is one we’ve been dealing with for decades — it’s been addressed via branch prediction, instruction sets, and ever-expanding caches. It’s been observed that we add one layer of cache roughly every 10 years, and we’re on track to keep that with Intel’s 128MB EDRAM cache on certain Haswell processors.

A new main memory with even half standard DRAM latency would give programmers an opportunity to revisit decades of assumptions about how microprocessors should be built. A new RAM technology that cut main memory accesses by an order of magnitude would be reason enough to reevaluate the entire balance of resources on a microprocessor. If accessing main memory was as fast as accessing the CPUs cache, you might not needcache on the CPU die or package at all — or at least, you wouldn’t need anything beyond L1 and maybe a small L2.

How long will it will it take to find a technology so fundamentally different and better from anything we have today that we can do away with the DRAM latency and power consumption bottleneck? Given how such a fundamental breakthrough would be vital to our ability to reach exascale computing and beyond, though, I hope it’s soon.

Server Storage 85% Faster w/o PCI Express

Latest advance in flash storage by changing system architecture and how flash storage is integrated are discussed in the article below. The potential for changes in flash storage architecture was already discussed in May 2012

 "Diablo’s Memory Channel Storage (MCS) architecture, expected to show up in servers shipping later this year, allows flash storage components to plug into the super-fast channel now used to connect CPUs with memory. That will slash data-access delays even more than current flash caching products that use the PCI Express bus...

Diablo estimates that MCS can reduce latencies by more than 85 percent compared with PCI Express SSDs (solid-state disks)...

The connection is designed to be used by many DIMMs (dual in-line memory modules) in parallel, so each component doesn’t have to relinquish the bus for another one to use it. That saves time, as well as CPU cycles that would otherwise be used managing the bus"


Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Flash breakthrough promises faster storage, terabytes of memory

Stephen Lawson, IDG News Service@sdlawsonmedia

• Jul 29, 2013 9:15 PM

In the ongoing quest for faster access to data, Diablo Technologies has taken what could be a significant next step.

Diablo’s Memory Channel Storage (MCS) architecture, expected to show up in servers shipping later this year, allows flash storage components to plug into the super-fast channel now used to connect CPUs with memory. That will slash data-access delays even more than current flash caching products that use the PCI Express bus, according to Kevin Wagner, Diablo’s vice president of marketing.

The speed gains could be dramatic, according to Diablo, helping to give applications such as databases, big data analytics and virtual desktops much faster access to the data they need most. Diablo estimates that MCS can reduce latencies by more than 85 percent compared with PCI Express SSDs (solid-state disks). Alternatively, the flash components could be used as memory, making it affordable to equip servers terabytes of memory, Wagner said.

Other than on-chip cache, the memory channel is the fastest route to a CPU, Wagner said. Not only do bits fly faster over this link, there are also no bottlenecks under heavy use. The connection is designed to be used by many DIMMs (dual in-line memory modules) in parallel, so each component doesn’t have to relinquish the bus for another one to use it. That saves time, as well as CPU cycles that would otherwise be used managing the bus, Wagner said.

The parallel design of the memory bus also lets system makers scale up the amount of flash in a server without worrying about diminishing returns, he said. A second MCS flash card will truly double performance, where an added PCIe SSD could not, Wagner said.

Diablo, which has been selling memory controllers for about 10 years, has figured out a way to use the standard DDR-3 interface and protocols to connect flash instead of RAM to a server’s CPU. Flash is far less expensive than RAM, but also more compact. The MCS components, which come in 200GB and 400GB sizes, will fit into standard DIMM slots that typically accommodate just 32GB or so of memory. The only adaptation manufacturers will need to make is adding a few lines of code to the BIOS, Wagner said.

Enterprises are more likely to use MCS as high-capacity memory than as low-latency storage, said analyst Jim Handy of Objective Analysis.

“Having more RAM is something that a lot of people are going to get very excited about,” Handy said. His user surveys show most IT departments automatically get as much RAM as they can for their servers, because memory is where they can get the fastest access to data, Handy said.

“Basically, you’d like everything to be in the RAM,” Handy said. Virtualized data centers, where many servers need to share a large set of data, need a shared store of data. But in other applications, especially with databases and online transaction processing, storage is just a cheaper and more plentiful—but slower—alternative to memory. “Everything that’s on the storage is there just because it can’t fit on the RAM,” he said.

To implement the MCS architecture, Diablo developed software and a custom ASIC (application-specific integrated circuit), which it will sell to component vendors and makers of servers and storage platforms. Flash vendor Smart Storage Systems, which earlier this month agreed to be acquired by SanDisk, will be among the companies using the MCS technology, Wagner said. In addition, a tier-one server vendor is preparing about a dozen server models with the technology and will probably ship the first of them this year, Walker said.

For the most part, Diablo doesn’t expect consumers or small enterprises to install MCS flash on their own computers. However, Diablo may work directly with enterprises that have very large data centers they want to accelerate, he said.

Using MCS flash to supplement DRAM would dramatically reduce the per-gigabyte cost of memory but also would allow for further consolidation of the servers in a data center, Wagner said. A large social networking company with 25,000 servers analyzed the MCS technology and said it would make it possible to do the same amount of work with just 5,000 servers.

That’s because the current DRAM-only servers can be equipped with just 144GB of memory, but MCS would allow each server to have 16GB of DRAM and 800GB of flash. With that much memory, each server can do more work so fewer are needed, Wagner said. Fewer servers would mean savings of space and energy, which would translate into lower costs, he said.

Integrating Flash in DDR4 DIMMs

Micron came up with a new product that adds flash memory on " the DDR4 bus in 18 months... leapfrogging today's solid state drives on PCI Express to open up new applications. ... The move gives flash a new position in the computer memory hierarchy, ahead of today’s solid state drives that ride the PCI Express bus.
The Hybrid DIMMs will be more expensive than SSDs but likely offer greater performance with memory access times measured in nano- rather than microseconds."
See more


This is an interesting product that leverages the speed of flash and places it higher in a computer system hierarchy. Intel has been working on developing other products that add flash memory closer to the microprocessor (see April 5, 2012 Flash is not just about storage )



Ron

Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

SSD, Flash, iPad, PC, Tablet, and Servers Architecture

The pace of implementing an appropriate eco-system of software and hardware for SSD, iPad, Servers, tablets, and PCs,  that would take into account flash memory is surprisingly slow. 

Just in a pc, NAND flash technology is slowly integrated in the PC's organization of hard drive, cache memory, and processor (see my April comments Flash is not just about storage  ).

The article below discusses Intel's perspective.

Intel's chief technology officer, Justin Rattner:
"the implications of what happens when main memory becomes non-volatile, Rattner said.
"Right now all extant architectures assume all [directly CPU-accessible] memory is volatile," he said, noting that Intel is looking at adding instructions to processors to help them correctly move data between cache and into persistent memory and back.

Along with processors, Intel is thinking about filing systems as well as it would be "ridiculous" to use conventional techniques on top of non-volatile memory. "Those [filing systems] are all optimised for when access times are in the tens of milliseconds, but [with non-volatile] now they're in the tens of nanoseconds.," Rattner said.

Ultimately, architectures will have to change because widespread use of non-volatile memory will make the "distinction between main memory and bulk memory... begin to disappear",

Ron
http://www.maltiel.com/


Intel: Non-volatile memory shift means chips need an overhaul

http://www.zdnet.com/intel-non-volatile-memory-shift-means-chips-need-an-overhaul-7000004221/
Summary: Processor architectures and filing systems will need dramatic redesigns to take advantage of upcoming non-volatile memory technologies, Intel has said.
By Jack Clark

Current processor and filing system designs must be revamped to get the most out of non-volatile memory technologies, Intel has said.
Though we are still a few years away from seeing a replacement for flash that will dominate the market, when it does chipmakers and filing system designers will need to alter their technologies to take advantage of the low latencies afforded by this new class of memory, Intel's chief technology officer, Justin Rattner, told ZDNet on Tuesday at the Intel Developer Forum in San Francisco.
"I'm reasonably confident that... non-volatile technologies will replace flash and bring non-volatile memory very close [to compute] with dramatic improvements in latency," he said. "Architectures will clearly have to react and respond to that."

Memory hierarchy

The jury is still out on exactly which technology will come to replace flash. It could be any one of phase change memory (which is currently being developed by IBM), memristors, which are being worked on by HP and Hynix, or spin-transfer torque, Rattner said.
Non-volatile memory can retain information without power — unlike RAM — and has fast access times, providing both huge power savings and the potential for much faster data transfer.

"Within probably the next three, four or five years we're going to have that memory, and we need to start now to look at the operating system issues and file system issues to take advantage of it," Rattner said.

When you change the memory hierarchy, it has huge knock-on effects on how computation works, he explained.

"Through most of the history of computing, we've assumed a persistent storage system — including the file system and virtual memory system — based on the characteristics of moving-head disks — devices with a very high access latency organised into fixed-sized blocks of thousands of bytes," Hank Levy, a professor of computer science and engineering at the University of Washington and non-volatile memory chip design researcher, told ZDNet on Thursday.

"These characteristics run very deep at every level of the software stack. These new memory technologies are fundamentally different both in their low access time and their fine-grained (byte-level) access."

If chip and filing system designers do not make fundamental changes to take advantage of new memory, "then we'll be missing an opportunity to really benefit from what these technologies can provide", Levy said.

Intel Labs research

To that end, Intel Labs is currently doing research about the implications of what happens when main memory becomes non-volatile, Rattner said.

"These new memory technologies are fundamentally different both in their low access time and their fine-grained (byte-level) access" — Hank Levy

"Right now all extant architectures assume all [directly CPU-accessible] memory is volatile," he said, noting that Intel is looking at adding instructions to processors to help them correctly move data between cache and into persistent memory and back.

Along with processors, Intel is thinking about filing systems as well as it would be "ridiculous" to use conventional techniques on top of non-volatile memory.
"Those [filing systems] are all optimised for when access times are in the tens of milliseconds, but [with non-volatile] now they're in the tens of nanoseconds.," Rattner said.
Ultimately, architectures will have to change because widespread use of non-volatile memory will make the "distinction between main memory and bulk memory... begin to disappear", he added.

Race to replace flash

Richard Coulson, director of the storage technologies group within Intel's technology and manufacturing group, pointed out that there is currently "a race" between spin-transfer torque, memristors and PCM to see which technology can be mass manufactured at a low enough price to be viable.
"We don't know which one of those or others will ultimately be cost effective," he told ZDNet on Wednesday. But when one of these comes in, "it changes the whole memory storage hierarchy".

Unfortunately, a lot of further development work depends on which non-volatile technology comes to dominate, and that is as yet unknown. "The base memory technology is the biggest wild card at the moment," Coulson said.

NAND Flash +DRAM Improves Memory Sys

Fusion io's blog discusses their collaboration with computer scientists at Princeton University

"  Volatile DRAM is faster—but much more expensive at high densities—than flash. NAND flash has much greater density than DRAM, and requires substantially less power to do its job. The Extended Memory library transparently tiers data between available DRAM in the system and the persistent NAND flash tier, making it much more affordable for organizations to greatly expand the size of their in-memory data sets without re-writing their applications."

See more about this partnership below:

Intel's approach regarding  PC memory organization is discussed in How SSDs conquered mobile devices and modern OSes




Other approaches for internal PC memory organizations were covered in a May blog -

Apple NAND Storage in Upcoming MacBook Pros


"There is a room for an overall personal computer hierarchy reorganization. Maybe Apple could lead here.
Currently in PC/ Mac we have a microprocessor (with some fast DRAM memory) connected to long term storage in flash SSD or HDD.
There would be many benefits to adding a small flash NAND between the microprocessor and the long term storage. Such computer hierarchy would benefit from the faster operation of the small flash NAND storage and its long term non volatile storage. It will also reduce power consumption.
The NAND memory could support the microprocessor operations or be used for storage of the operating system."


Ron




Princeton Scientists Partner On DRAM Innovation

http://www.drdobbs.com/tools/princeton-scientists-partner-on-dram-inn/240003554
By Adrian Bridgwater, July 11, 2012


Fusion-io technology now extends memory from DRAM to NAND flash



A collaboration between computer scientists at Princeton University and Fusion-io has led to the development of a new Extended Memory subsystem to be made available as part of the firm's own brand SDK.





The Extended Memory subsystem works to extend system memory from DRAM onto flash, providing what has been described as "much more high-performance memory capacity" than currently possible with DRAM alone.





The firm's message to software programmers is that this is an extended memory option for developers who chose to customize applications to leverage ioMemory technology. Applications can then extend their in-memory data from DRAM onto ioMemory, which — generally speaking — should also save money as DRAM is argued to be cost-prohibitive, not persistent, and limited in capacity.





Will this garner interest from developers attracted to the benefits of storing all data in-memory, especially to meet the needs of web-scale, cloud, and big data computing? It is an attractive sounding option for sure, but success here will be based on whether this Extended Memory's ability to intelligently tier data between available DRAM in the system and the persistent NAND flash tier works as well as described.



"The Fusion ioMemory architecture is uniquely suited to innovation like the Extended Memory subsystem," said Chris Mason, Fusion-io director of kernel engineering and principal author of the Btrfs filesystem for Linux. "Since Fusion ioMemory has moved beyond legacy disk-era protocols, we can integrate new features like the Extended Memory subsystem to truly advance application performance for enterprise computing in ways that are simply not possible with traditional SSDs."







The Extended Memory subsystem dynamically moves frequently accessed data pages into memory on-demand while migrating rarely accessed data pages from DRAM into ioMemory. This says Fusion-io allows developers to simplify application design by assuming that entire datasets are in-memory, without the costs associated with DRAM purchase and operation.





Application developers are able to further tune performance through software development kit tools that lock selected pages into DRAM, giving access to NAND flash as memory, instead of treating it as an extension of disk storage. This allows legacy applications to scale up with flash memory, instead of scaling out, boosting performance and reducing total cost of ownership.

Microsoft: Million+ PC, Laptop, DRAM failures

The report below shows the results of Microsoft's analysis of the crash data sent back to Redmond from over a million PCs.

It is interesting that laptops didn't crash as often as desktops in the study. This is especially surprising considering that 1/3 of laptops fail in the first 3 years (article I read about a year ago).






Ron




Microsoft analyzes over a million PC failures, results shatter enthusiast myths

http://www.extremetech.com/gaming/131739-microsoft-analyzes-over-a-million-pc-failures-results-shatter-enthusiast-myths

By Joel Hruska on June 26, 2012 at 4:10 pm

Researchers working at Microsoft have analyzed the crash data sent back to Redmond from over a million PCs. You might think that research data on PC component failure rates would be abundant given how long these devices have been in-market and the sophisticated data analytics applied to the server market — but you’d be wrong. According to the authors, this study is one of the first to focus on consumer systems rather than datacenter deployments.



What they found is fascinating. The full study [1] is well worth a read; we’re going to focus on the high points and central findings. There are two limitations to the data collected that we need to acknowledge. First, the data set we’re about to discuss is limited to hardware failures that actually led to a system crash. Failures that don’t lead to crashes are not cataloged. Second, the data presented here is limited to hardware crashes, with no information on the relative frequency of software to hardware crashes.



CPU overclocking, underclocking, and reliability

When it comes to baseline CPU reliability, the team found that the chance of a CPU crashing within 5 days of Total Accumulated CPU Time (TACT) over an eight month period was relatively low, at 1:330. Machines with a TACT of 30 days over the same 8 months of real-time have a higher failure rate, of 1:190. Once a hardware fault has appeared once, however, its 100x more likely to happen again, with 97% of machines crashing from the same cause within a month.



Overclocking, underclocking, and the machine’s manufacturer all play a significant role in how likely a CPU crash is. Microsoft collected data on the behavior of CPUs built by Vendor A and Vendor B (no, they don’t identify which is which). Here’s the comparison chart, where Pr[1st] is the chance of the first crash, Pr[2nd1] the chance of a second subsequent crash, Pr[3rd2] the chance of a third failure. In this case, overclocking is defined as running the CPU more than 5% above stock.

Are Intel chips just as good as AMD chips? At stock speeds, the answer is yes. Once you start overclocking, however, the two separate. CPU Vendor A’s chips are more than 20x more likely to crash at OC speeds than at stock, compared to CPU Vendor B’s processors, which are still 8x more likely to crash. The report notes that “After a failure occurs, all machines, irrespective of CPU vendor or overclocking, are significantly more likely to crash from additional machine check exceptions.” The team doesn’t break out overclocking failures by percentage above , but their methodology does prevent Turbo Boost/Turbo Mode from skewing results. Does overclocking hurt CPU reliability? Obviously, yes.



So what about underclocking? Turns out, that has a significant impact on CPU failures as well.

As you can see, underclocking the CPU has a significant impact on failure rates. The impact on DRAM might seem puzzling — the researchers only reference CPU speed as a determinant of underclocking, rather than any changes to DRAM clock rate. Our guess is that the sizable impact on DRAM is caused by a slower CPU alone rather than any hand-tuning of RAM clock, RAM latency, or integrated memory controller (IMC) speed. IMC behavior varies depending on CPU manufacturer and product generation in any case, while the size of the study guarantees that a sizable number of Intel Core 2 Duo chips without IMCs would still been part of the sample data.



Laptops vs. desktops, OEM vs. white box

Ask enthusiasts what they think about systems built by Dell, HP, or any other big brand manufacturer, and you aren’t likely to hear much good. Actual data proves that major vendors actually have fewer problems than the systems built by everyone else. The researchers identified the Top 20 computer OEMs as “brand names” and removed overclocked machines from the analysis of the data. Only failure rates within the first 30 days of TACT were considered among machines with at least 30 days of TACT. This is critical because brand name boxes have an average of 9% more TACT than white box systems, which implies that the computers are used longer before being replaced.

White box systems don’t come off looking very good in these comparisons. CPUs are significantly more likely to fail, as is RAM. Disk reliability remains unchanged.



How about laptops? The researchers admitted that they expected desktops to prove more reliable than laptops due to the rougher handling of mobile devices and the higher temperatures such systems must endure. What they found suggests that laptop hardware is actually more reliable than desktop equipment, despite the greater likelihood that mobile systems will be dropped, sat on, or eaten by a bear. Again, overclocked systems were omitted from the comparison.

Desktops don’t come off looking very good here despite their sedentary nature. The team theorizes that the higher tolerances engineered into the CPU and DRAM, combined with better shock-absorbing capabilities in mobile hard drives may be responsible for the lower failure rate. The difference between SSDs and HDDs was not documented.



More data needed

The limitations of the study are such that we can’t draw absolute conclusions from this data, but they suggest a need for better analysis tools and indicate that adopting certain technologies, like ECC, would help improve desktop reliability. It’s one thing to say that overclocking hurts CPU longevity; something else to see that difference spelled out in data. The impact of underclocking was also quite surprising, this is the first study we’re aware of to demonstrate that running your CPU at a lower speed reduces the chance of a hardware error compared to stock.



The Microsoft team conducted the research as one step towards the goal of building operating systems and machines that are more tolerant of hardware faults. The fact that systems which throw these types of errors are far more likely to continue doing so strikes at the idea that such problems are random occurrences, as does much of the reliability information concerning DRAM.



The report throws doubt on a good deal of “conventional” wisdom and implies reliability is rather sorely lacking. More data is needed to determine why that is, and to correct the problem.




Endnotes

full study: http://research.microsoft.com/apps/pubs/default.aspx?id=144888

: http://www.extremetech.com/wp-content/uploads/2012/06/AMD-vs-Intel.png

: http://www.extremetech.com/wp-content/uploads/2012/06/Underclocking.png

: http://www.extremetech.com/wp-content/uploads/2012/06/Brand-vs-whitebox.png

: http://www.extremetech.com/wp-content/uploads/2012/06/Desktops-vs-Laptops.png

Apple NAND Storage in Upcoming MacBook Pros

There is a room for an overall personal computer hierarchy reorganization. Maybe Apple could lead here.

Currently in PC/ Mac we have a microprocessor (with some fast DRAM memory) connected to long term storage in flash SSD or HDD.

There would be many benefits to adding a small flash NAND between the microprocessor and the long term storage. Such computer hierarchy would benefit from the faster operation of the small flash NAND storage and its long term non volatile storage. It will also reduce power consumption.

The NAND memory could support the microprocessor operations or be used for storage of the operating system.

There were rumors a couple of years ago about Intel working on such system. It never made it out due to legacy software optimization issues.

Ron





Apple likely to use NAND storage in upcoming MacBook Pros, analyst says
http://www.appleinsider.com/articles/12/05/30/apple_likely_to_use_nand_storage_in_upcoming_macbook_pros_analyst_says.html
By Mikey Campbell
Published: 05:35 PM EST (02:35 PM PST)

A research analyst from Barclays believes that Apple's success in NAND adoption will drive the company to use the technology in a rumored refresh of its MacBook Pro line, a move that will disrupt the business of of both hard drive and PC makers.

In a note to investors released on Wednesday, Ben Reitzes of Barclays Equity Research said that the adoption rate of Apple devices using SSDs, along with a continuing move to cloud computing, will push consumer laptop demand toward flash-based storage.

Perhaps the single greatest setback to flash adoption is that the price of solid state solutions grossly outweigh comparable HDDs, keeping the technology out of reach for everyday consumers. This cost ratio may tilt in the physical hard drive's favor, however consumers have recently started giving up storage space and low cost for design and performance benefits, evidenced by the success of the thin and light MacBook Air.

Reitzes believes that the advent of cloud computing will help ease consumers in the transition from physical drives to flash by offloading storage to servers, thus diminishing the need for pricey high-capacity NAND drives. Apple's iCloud is already well in-place and has the potential of filling offsite storage needs if the company chooses to move to a NAND-heavy laptop lineup.

For these reasons, the analyst expects Apple to reveal a NAND-equipped MacBook Pro as well as MacBook Airs with increased storage options in the near future.

"We believe these products combined can ramp quarterly demand for Macs by up to 1 million incremental units on a run rate basis - taking over a point of share from HDD-based PCs," Reitzes said.

He goes on to say that an estimated 5 to 10 percent of notebook PC sales have been cannibalized by NAND-carrying iPads and iPhones, further impacting HDD demand for PCs. The move to portable products has been dubbed as the "post-PC era," as consumers begin to replace computers with tablets and handset. Interestingly, this trend toward flash in consumer devices is seen as fueling data growth, which helps to augment sales of enterprise-class HDDs.