14nm FinFETs Technolgy

In the upcoming IEDM Intel will talk more about their 3D transistors using FinFET for the 14nm generation (see below). 

"Intel will reveal its processing secrets including its doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in mitigation of variation, its use of two levels of air-gap-insulated interconnects at 80-and-160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics"

Also IBM will discuss at IEDM adding SOI to FinFETs, which reduce their capacitance. SOI has been used by IBM for other processes, however it complicate designing circuits on the chips.

See more about FinFETs from May 2011 at - Tutorial: Intel 22nm 3D Tri-Gate FinFETs Transistors  

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consultin

Intel, IBM Dueling 14nm FinFETS

IEDM reveals diametrically opposed approaches

R. Colin Johnson

10/21/2014 06:26 PM EDT 

PORTLAND, OR — Every digital semiconductor manufacturer and foundry in the world is trying to build 3D FinFETS that rival Intel, which is so far leading the pack by several years. Hot on Intel's heels is IBM, which just signed a deal to turn its fabs over to GlobalFoundries (which has already licensed Samsung's FinFET process that, according to Rick Doherty, research director of The Envisioneering Group, told EE Times stems from early IBM/GlobalFoundaries discussions). TSMC, AMD, Freescale, and others claim to be hot on Intel's and IBM's trail, but have yet to prove it.
With that background, the "dueling technologies" session over FinFET designs being held at the IEEE International Electron Devices Meeting (IEDM, December 15 until December 17, 2014, in San Francisco) looks to be a knock-down, drag-out fight.
"The IEEE's use of the phrase 'dueling technologies' is right!" Doherty told us. "Engineers at IEDM will pass muster on the amazing advances of IBM and Intel first with applause, and later, with purchase orders."

The size of transistor gates and "fins," especially to interconnection, were reduced by more than a third from the previous generation of technology.
(Image: Intel)

Envisioneering believes the IBM FinFET details to be revealed at IEDM lean towards bolstering the Samsung/GlobalFoundaries FinFET technologies already being integrated into Global’s 14 nanometer processes.
"The combinations of dense memory, scalable power budgets and SoCs up to 600 square millimeters strongly point to these IEDM features being available on IBM silicon from Global," Doherty told us. "And possibly available to broader Global customers. What is not yet known is whether these technologies will be build upon the Samsung suite, or might become an alternative FinFET offering from Global."

Built on a fully depleted SOI technology base, IBM's 3D, FinFET architecture retains the advantages of SOI over bulk-based planar technologies, which IBM claims is a simpler manufacturing process, with isolation by structure, not doping, low-voltage operation, and lower power.
(Image: IBM)

Either way, Doherty told us that the winners here are customers of both Global and Intel.
"At the IEDM, system and silicon architects will start determining the best applications and markets for each. Intel has given a clear commitment to its novel FinFET designs," Doherty told us. "Global’s choice of two FinFET techniques will likely attract SoC, mobile and high performance users looking for custom solutions."
The biggest difference between IBM's and Intel's approach is that Intel -- as usual -- has taken the traditional bulk silicon approach to developing its FinFET design resulting in a a two- to four-year lead on its competitors in perfecting its approach. Intel has been manufacturing FinFETS in volume since 2011 starting with its 22nm Ivy Bridge and later Haswell micro-architecture processors. More recently it announced successfully transferring of the technology to its 14nm Broadwell micro-architecture which it is the centerpiece for its latest Core M processor family.
IBM, on the other hand, has take a more experimental approach using more expensive silicon-on-insulator (SOI) substrates that it claims simplify the manufacturing process, allow lower-voltage operation, which means lower-power chips in the long run.
FinFETS were designed to mitigate the leakage effect of short-gate transistors, and have proven to work with or without SOI. By wrapping the gate around the "fin" channel it is possible to fully or nearly-fully deplete the channel when its off leaving very little leakage current to overheat chips.
According to IEDM, Intel will reveal its processing secrets including its doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in mitigation of variation, its use of two levels of air-gap-insulated interconnects at 80-and-160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics; an embedded 140Mb SRAM memory with a tiny cell size of 0.0588 square micrometers. The fully saturated drive currents are significantly higher than for Intel's 22nm first-generation FinFETs (improvements of 15% for NMOS and 41% and PMOS transistors. Intel will also discuss how it achieved such high-aspect ratio rectangular fins only 8nm wide and 42nm high, according to IEDM. All Intel transistors are operating at a supply voltage of only 0.7 volts.
IBM counter argument
IBM will describe its SOI approach to building 14nm FinFETs, emphasizing that its insulated substrates are worth the extra money the wafers cost because of the processing steps they reduce to isolated devices from one another. Its latest 14nm FinFETs are 35% faster than its planar 22nm transistors and use an operating voltage of 0.8 volts.
IBM will also claim the world's smallest and densest DRAM cells ever demonstrated, taking up just 0.0174 square micrometers. IBM will also describe its unique dual-workfunction process, for both low power and high speed, by virtue of optimizing the threshold voltages of both NMOS and PMOS transistors without mobility degradation in the channel, according to IEDM.
IBM will also brag about its 15 levels of copper interconnect to distribute power and clocks across an entire 600 square millimeter complex SoC for everything from video game consoles to corporate-caliber data centers.
Intel's paper will be called "A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM Cell Size."
IBM's will be called "High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 Embedded DRAM and 15 Levels of Cu Metallization."
— R. Colin Johnson, Advanced Technology Editor, EE Times

IBM Selling Foundry Fabs

The article below discuss IBM announcement that it is selling its manufacturing operations. It will impact SOI (Silicon on Insulator), a process  that IBM specialized in.

It is not likely that Intel will buy an existing fab. Intel always duplicates an existing process in a current fab when they build a new fab 

It is just another example of consolidation chip manufacturing see in March 2012 Moore's Law End? (Next semiconductors gen. cost $10 billion

" chip industry without IBM will be a diminished industry."

IBM has been number 10 in foundry ranking for several years ( Top Semiconductor Ranking 2012 (Sales, Growth) 

More recent IBM dropped to number 11 in ranking (Top 13 Foundries Account for 91% of Total Foundry Sales in 2013)

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

IBM fabs for sale – the semiconductor shockwave

 

david manners

 

10th February 2014

Following the semiconductor shock of IBM pulling out of chip manufacturing, David Manners considers who could buy and run the IBM fabs, whose processes include SOI and SiGe, and which supply manufacturing process technology to half the world’s major companies: Samsung, GloFo, UMC, ST, Renesas, NEC, Freescale, Toshiba and Infineon.

The biggest shockwave the semiconductor industry has had for years is the IBM announcement that it is pulling out of chip manufacturing.

IBM CEO Ginni Rometty has decided that IBM’s future is in software and services and chip manufacturing clearly doesn’t fall in either of these categories .

Moreover IBM’s chip manufacturing business lost $130 million last year and is slated to lose another $130 million this year while the capital costs to stay in the game are $5 billion a factory and rising.

That’s one way of looking at it.

The other way of looking at it is that IBM has been a stalwart of the world semiconductor industry, inventing the DRAM, mastering SiGe, SOI and much more besides and supplies manufacturing process technology to half the world’s major companies: Samsung, GloFo, UMC, ST, Renesas, NEC, Freescale, Toshiba and Infineon.

It is shocking to think IBM’s legendary R&D operation may be curtailed but, without the justification of a business outlet for its innovations, it may be.

One rather assumes that the obvious candidates for buying IBM’s fabs have already been tapped and that the announcement that Goldman Sachs has been appointed to look for a buyer for the fabs is to find an unobvious candidate.

The obvious candidates are Intel, TSMC, GloFo and Samsung.

However, Intel has net cash of only $7 billion and makes only CMOS chips, while IBM’s capacity includes processes like SOI and SiGe which Intel won’t need and the IBM fabs are not as advanced as Intel’s.

TSMC says it doesn’t want to operate foreign fabs; GloFo’s owners are said to be getting fed up with their capital-greedy chip investment and may not want to expose themselves further to the chip industry; Samsung already has as much operational and planned capacity in the USA as it needs.

So how about the non-obvious candidates?

Suggestions have been that Apple could enter into a jv with IBM to run the fabs. This would involve Apple putting a lot of money in to upgrade the fabs to the latest processes, but Apple has lots of money and IBM has the latest processes.

TowerJazz is another suggestion. The company has just formed a jv with Panasonic in which TowerJazz has a 51% share and which will own three Panasonic fabs in Japan.

The Panasonic deal gives TowerJazz’s already impressive array of specialty processes the addition of Panasonic’s specialty flows such as High Definition FSI for sensors and high voltage SOI power management technologies.

If TowerJazz now added IBM’s specialty processes like SiGe and SOI to its stable, it would become the world’s No.1 specialty fab.

Another suggestion is China. China has been trying, unsuccessfully, to build an indigenous chip industry for 30 years. Following the successful integration of IBM’s PC business into Lenovo, followed by the recent sale of IBM’s x86 server business to Lenovo, it would seem quite logical that a sale of IBM’s chip manufacturing would be to China.

Of course the European authorities, wedded to the idea of gaining 20% world market share in IC manufacturing, may see the opportunity to acquire IBM’s world-class process development capabilities as a sufficient reason to buy the fabs. IBM’s proficiency in SOI would give a boost to the European-developed FD-SOI process.

Then, of course, there are other emerging national tech players like Brazil and India who could see this as a once in a lifetime opportunity to acquire the basis for a chip industry.

Whatever the outcome of this, a chip industry without IBM will be a diminished industry.

IBM: Fab Future Beyond FinFETs

The Common Technology Platform and other vendors have been lagging Intel in process development and  integration for several years. In a recent Common Platform Technology Forum, IBM presented their latest effort to catch up - vision of Fab future.
"IBM spotlights double patterning tricks with immersion lithography, showed advances in fully depleted silicon-on-insulator".

 "IBM, GloFo and Samsung now claim they have the lion's share of today's 32/28 nm, high-K metal gate capacity."
While they are claiming to have the fab capacity lead for 28nm HKMG process, Intel, TSMC, and other foundries would feel differently.

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

FinFET Layout Design Rules and Variability

It is not simple to design circuits with FinFET transistors. Layout, 3D dimensions, and shape considerations are described in the article below. Some additional information about Intel's 22nm 3D Tri-Gate FinFETs Transistors.








Ron
http://www.maltiel-consulting.com/



FinFET structure design and variability analysis enabled by TCAD

Victor Moroz, Synopsys Inc.

10/8/2012 10:14 AM EDT

The introduction by Intel of FinFET transistors at the 22nm mode culminates many years of research and development of a replacement transistor to the immensely successful planar MOSFET whose progressive miniaturization is largely responsible for the electronics revolution. The need for a successor to the planar MOSFET had long ago been identified. Starting with the 90nm process node, improved transistor performance was achieved with the introduction of stress into the transistor channel in a way that boosts the speed of the electrons and holes traveling within it. However, controlling the transistor leakage in the off-state became progressively more difficult. Keeping the electrons and holes under the electrostatic control of the gate electrode is key to controlling leakage current, but a number of so-called short channel effects undermine the gate control. The introduction of high-k dielectrics as the gate insulator at the 45nm process node effectively extended the life of the planar MOSFET for another two process nodes, but by the 22nm process node the planar MOSFET could hardly offer an attractive balance of performance and leakage.


Intel’s FinFETs thus mark the first fundamental change in transistor architecture since the time when the MOSFET replaced the bipolar transistor as the transistor of choice for logic applications. Its performance improvements over the preceding process node (see table) are a clear indication of the promise this technology holds. Although the manufacturing of FinFETs is more complex than manufacturing of its planar predecessor, Intel’s introduction is a testament to the inevitability of these devices....   More at FinFET Layout Design and Variability

Intel's 14nm Process and Manufacturing Roadmap

With foundaries venturing into the FinFET devices it is interesting to see Intel's direction.


The article below with Mark Bohr, senior fellow at Intel, review the road map pertaining to a wide range of manufacturing and design issues. Some of the key points in the article are:

* Intel is sticking with bulk CMOS instead of SOI.

* FinFET transitors are scalable to 14nm process.

* "3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you’re trying to serve. For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution"

Additional information about Intel's 22nm at Tutorial: Intel 22nm 3D Tri-Gate FinFETs Transistors and at Intel’s 22-nm Tri-gate Transistors Exposed


Ron
http://www.maltiel-consulting.com/



Deep Inside Intel
By Ed Sperling

Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends.


SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel?

Bohr: For a process module as critical as lithography, Intel always has more than one option we pursue. In this era, the options are either EUV or 193nm immersion with multi-patterning.


SMD: How about directed self-assembly?

Bohr: That’s not a universally usable approach. You still need to define some layers with direct patterning, not a self-assembly technique. That’s a niche direction that will not replace these mainstream lithography techniques, but there may be some layers where it can complement the normal patterning techniques.


SMD: What’s your opinion about the future of the foundry business?

Bohr: The traditional foundry model is running into problems. In order to survive, the foundries will have to become more like an integrated device manufacturer. Even some of the chief spokespeople for the foundries have said something similar. The foundry model worked well when traditional scaling was being followed and everybody knew where we were headed. In this era, where you continually have to invent new materials and new structures, it’s a lot tougher being a separate foundry and maskless design house. Being an IDM, we have design and process development under one roof. That’s really a significant advantage.


SMD: Can even Intel afford to be an independent IDM? The cost of building state-of-the-art fabs at future nodes is astronomical.

Bohr: Yes. We have the volume and the products that can fill multiple fabs.


SMD: But you’ve also opened up your fabs to at least a couple customers. Are you planning on extending that? ,

Bohr: Our motivation is that we know we have great process technology, and partnering with other strategic companies can be a win-win situation. We can sell our technology and make more money off what we’ve developed, and they can have some very compelling products. It’s not Intel’s goal to be a general-purpose foundry, but we will be partnering where it makes strategic sense.


SMD: Is Intel sticking to bulk CMOS or will move to new materials such as fully depleted SOI?

Bohr: We see more advantages in bulk than SOI. I won’t say SOI won’t be in the future. There may be some device structure that is better done in SOI than bulk. But I don’t see than happening right now. When we first announced that we were making TriGate or finFET devices at 22nm, we said we’re making these devices on SOI, as well. But we think there are cost advantages to doing TriGate on bulk rather than SOI. That’s our plan for the foreseeable future.


SMD: What comes after the current finFET?

Bohr: The finFET is scalable to 14nm.


SMD: But if you’re at 22nm, 14nm isn’t very far away, so you’ve got to be working on the next step.

Bohr: For Intel, you’re right. For other companies, it’s many years away. For 10nm, which is where I’m spending most of my time these days, I know we have a solution. I can’t elaborate at this point.


SMD: At 10nm aren’t you running into quantum effects?

Bohr: Everything gets different and tougher, but the problems are solvable—at least at that generation.


SMD: How far ahead can you see?

Bohr: I know we can get to 10nm. Beyond that, our research group is working on solutions for 7nm and 5nm. I have confidence we’ll have solutions for those. But by the time we’re down to 5nm we’ll be looking at non-familiar devices and device structures. That’s what we’ll have to do to get down to that level.


SMD: Where do stacked die fit into your roadmap?

Bohr: 3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you’re trying to serve. For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution.


SMD: Along those lines, does Intel see the smart phone and small mobile device market as a key direction?

Bohr: Intel is very serious about getting into the smart phone and tablet markets. We are a very different company from what we were five or six years ago. We are developing process technologies, but also products, that span a much wider range of performance and power than anywhere in our history. We’re not just after the high-performance desktop. We’re developing products that support 100-watt server chips down to sub-1 watt smart phone chips.


SMD: There are a number of interesting techniques Intel is working with, such as near-threshold computing. How will power management start changing inside these chips?

Bohr: When you’re talking about developing a smart phone chip that is ultra low power that also provides improved performance features that the market expects, you have to pull every trick out of the bag. You need great transistor technology, great package technology, great CPU architectures, the ability to turn off parts of the chip when you don’t need them so you’re saving power, the software links with the chip design so the software knows when to throttle power down. You need transistors, CPU architecture and software to be effective in that space.


SMD: How many cores will be required in the future?

Bohr: It depends on the market. In the server market, the more cores you can pack on the better. But in desktops, laptops and smart phones, there’s probably a limit to how many cores are practical. It’s not one. It’s probably several.


SMD: But less than eight?

Bohr: Yes, probably less than eight. But when you talk about the number of cores and computing engines, it depends on whether you’re dealing with traditional computing tasks where four cores are better than two cores. If you’re talking about execution engines in a graphics processor, clearly you want more cores.


SMD: What does this do for Intel’s platform strategy, particularly as you go after many markets with very specific needs?

Bohr: Even for Intel there are probably an optimal number of chip designs. It’s not like in the past where we tried to make one size fit all or have one chip serve multiple markets. But on the other hand, trying to design and manufacture dozens of very different designs in a generation is also impractical. There’s an optimal number of designs, although I don’t know what that number is, that can best meet the market requirements. You want to make as few iterations between the different designs as you can or re-use the cores or some of the circuit blocks between the different chips so you’re not completely redesigning it.


SMD: Are there other materials being considered for transistors?

Bohr: Our research group has been publishing papers about using 3-5 materials http://en.wikipedia.org/wiki/List_of_semiconductor_materials for the channels. You deposit indium phosphide or gallium arsenide layer on top of silicon to make a transistor on the surface. It’s still a silicon wafer, but you’re looking at depositing more exotic materials. That’s new and different and it may happen, but it’s not yet fully resolved how good that approach may be.


SMD: Has the priority for what you’re designing into a chip changed? Is it still all about performance, or has power overtaken that?

Bohr: Ten or 15 years ago, performance was the main goal in developing a new process technology. That really has gone away as the No. 1 priority. We still strive to provide a performance boost with each new technology, but there’s much more emphasis on improving power or efficiency on each new generation. We do that by reducing active power for the work a chip does. That’s a much more important goal for us today. Part of the reason is that the market has shifted from desktop applications to more mobile products. The first transition was from desktops to laptops. Now the move is to put things into smart phones. Today’s consumer wants computing power he can hold in his hand in the form factor of a smart phone and a tiny battery. He wants the performance he had on his laptop only three or four years ago. That’s what we shoot for.


SMD: That shifts the biggest challenge to the architecture, right?

Bohr: Yes. Whether it’s low-power, low-leakage transistors or a more efficient core architecture—or linking that with more efficient software.


SMD: What becomes the next big bottleneck?

Bohr: We have lots of challenges. Lithography is the key challenge in making transistors smaller. Whether EUV will happen on time or we have to extend immersion using multiple patterning. But when you make transistors smaller they don’t become less leaky. In fact, the opposite is true. You have to continually invent new structures and materials to allow feature-size scaling, which is critical for active power reduction and for cost.



SMD: But wires don’t scale well. How do you deal with that?

Bohr: RC delay gets worse as you scale, compared with transistors, which tend to get faster as you scale down. The industry has had 20-plus years of struggling with that problem. One way we’ve addressed that is that we’re no longer striving for very high operating frequency, especially in the phone market where 2 or 2.5GHz would probably be sufficient. That’s one advantage. The other advantage is that the average size of the chips is smaller in these laptop and cell phone applications so you don’t have interconnects traveling a long distance across a large chip. Instead, it’s a more compact chip so the signals don’t have to go as far. But even with those chips, we still have a challenge of performance from the interconnect. We have to be clever about what pitches we choose. Some of the lower layers are dense pitch, where density is important. Some of the upper layers are coarser pitch, where performance is important. We’re also continuing to drive down interconnect capacitance by employing lower-k dielectrics.


SMD: Is the interconnect becoming more problematic?

Bohr: If you talk to a designer 10 years ago you would have heard the same thing. Maybe now they’re saying, ‘This time we’re really serious.’


SMD: How about new interconnect technology?

Bohr: It’s hard to replace copper and low-k other than by making lower k. But at least in the low-power cell phone market, stacking chips does help to minimize some of the interconnect issues, particularly between the logic and the memory chips.


SMD: You’re referring to through-silicon vias?

Bohr: Yes.


SMD: So if Intel is planning to get into that market, the company is experimenting with that technology right now?

Bohr: Yes, and we’ve been public about exploring TSV and 3D technology for a couple years. Although there are some challenging technology aspects, the real issue is cost. Doing TSVs and stacking chips—especially these custom Wide I/O chips—is expensive. So this might be a better engineering solution in terms of density, performance and power, but will the market bear the added cost? Not all markets will bear the higher cost.