3D Flash Race:Intel vs Samsung

Following Samsung development of V- NAND Intel introduce their version of 3D NAND (see below). One of the benefits of 3D flash memories is the capability of using larger design rules such as 30-40 nm instead of scaling the design rules to smaller than 20nm.

One of the key problem of shrinking to smaller design rules than 20nm is the cost and complexity of multi-patterning photolithography and EUV lithography difficulties (ASML: Next-gen chipmaking tool ready forproduction in 2016 ). In addition, the reliability of the flash memory degrades when the memory cells become too close to each other.

"Samsung consciously went from a 24-layer 128Gbit MLC die to a 32-layer 86Gbit MLC die. In other words, Samsung could have upped the die capacity to ~170Gbit by just adding the extra layers, but the company chose to go with a smaller die instead. Smaller capacity dies have advantages in performance (higher parallelism) and applicability because eMMC/microSD devices have very strict die size constraints, "

Samsung only use 24 layers in fabricating the chips in order to increase the yield, which reduces the cost of working dies on each wafer. Adding layers that has to be manufactured with precise alignment and low defect density lengthen the learning curve of fabricating working dies. Intel is trying to catch up with Samsung which is already making the second generation of 3D NAND (Samsung 3D Process Pioneers Next Gen Semiconductor Devices ).


Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Intel's 3D NAND to Ship in H2'15: 256Gbit Die

 & 32 Layers

by Kristian Vättö on November 25, 2014 5:20 AM EST

Last Thursday in its annual Investor Meeting Intel revealed the first details of its 3D NAND technology and announced that it will begin the shipments of 3D NAND in the second half of 2015. While Intel's investment in 3D NAND hasn't been a secret, the company has been relatively quiet about any specifics and the vital specs such as the number of layers and die capacity have remained unknown. In Thursday's webcast, Rob Crooke, Senior VP and General Manager of Intel's non-volatile memory group, disclosed that Intel's first generation 3D MLC NAND die will be 256Gbit (32GB) in capacity and will consist of 32 layers. The technology also enables a 384Gbit (48GB) TLC (3-bit-per-cell) die as we have learned over the years.

Intel claims that its 3D NAND is the most cost effective on the market and bases this on the fact that its die is 256Gbit whereas Samsung's is only up to 128Gbit at the moment. I'm not sure if I buy Intel's claim because while it's true that a higher capacity die results in higher array efficiency (i.e. peripheral circuitry takes less area), Samsung consciously went from a 24-layer 128Gbit MLC die to a 32-layer 86Gbit MLC die. In other words, Samsung could have upped the die capacity to ~170Gbit by just adding the extra layers, but the company chose to go with a smaller die instead. Smaller capacity dies have advantages in performance (higher parallelism) and applicability because eMMC/microSD devices have very strict die size constraints, so that might be a part of the reason why Samsung's strategy is so different from Intel's and Micron's. 

As the graph above shows, Intel's/Micron's NAND dies have historically been larger than the competitors', so the die capacity alone isn't enough to dictate whether Intel's 3D NAND is more cost efficient than Samsung, especially because both have 32 layers. Unlike Samsung, Intel didn't reveal the lithography that is used to manufacture the 3D NAND, but I would say it's safe to assume that the lithography is in the order of 30nm or 40nm because the whole idea of 3D NAND is to move away from multi-patterning to cut costs and with today's technology the smallest pitch of single-patterning is somewhere between 30nm and 40nm. Either way, it will be very interesting to see how Intel's 3D NAND stacks up against Samsung's because there are also some structural differences that affect the production cost as well as performance and endurance, but I'll save the structural analysis for a future article.

Intel said that 3D NAND technology will enable +10TB SSDs in the 'next couple of years', but it wasn't clear whether that is with first generation 3D NAND or some later generation with more layers and higher die capacity. Currently Intel's lineup tops out at 2TB (P3700 & P3600) with a 128Gbit die, so the 256Gbit die alone isn't enough to bring the capacities above 10TB. With effective controller development it should certainly be possible to build a 10TB SSD with a 256Gbit die, although I'm still inclined to believe that Mr. Crooke was referring to second or third generation 3D NAND with his statement. 

Similar to Intel's previous NAND efforts, 3D NAND has been jointly developed with Micron and will most likely be manufactured in the co-owned Utah plant as Intel sold its share in other fabs a couple of years ago. Interestingly enough, Mr. Crooke said that they also have the ability to bring 3D NAND production to an Intel fab, although to me that sounded more like a statement of technological possibility rather than a hint of future strategy. I wouldn't rule it out, though, but like Mr. Crooke said in the Q&A, Intel needs to have significant competitive advantage for it to make sense. In the past Intel's NAND technologies have generally been slightly ahead of the rest of the industry, but at least as of now Intel doesn't seem to have any substantial advantage in 3D NAND technology as Samsung is already shipping a 32-layer die and will likely ship a 48-layer die before Intel ships its 32-layer product.

All in all, we'll likely get more crumbs of information as the second half of 2015 gets closer. Given Intel's recent SSD strategy, I expect 3D NAND to first find its way to enterprise-class SSDs, but we'll see soon enough.