Following Samsung development of V- NAND Intel introduce their version of 3D NAND (see below). One of the benefits of 3D flash memories is the capability of using larger design rules such as 30-40 nm instead of scaling the design rules to smaller than 20nm.
One of the key problem of shrinking to smaller design rules than 20nm is the cost and complexity of multi-patterning photolithography and EUV lithography difficulties (ASML: Next-gen chipmaking tool ready forproduction in 2016 ). In addition, the reliability of the flash memory degrades when the memory cells become too close to each other.
"Samsung consciously went from a 24-layer 128Gbit MLC die to a 32-layer 86Gbit MLC die. In other words, Samsung could have upped the die capacity to ~170Gbit by just adding the extra layers, but the company chose to go with a smaller die instead. Smaller capacity dies have advantages in performance (higher parallelism) and applicability because eMMC/microSD devices have very strict die size constraints, "
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