After some delays and uncertainty in past years, the 3D NAND market is finally heating up.
In 2013 and 2014, Samsung was the only vendor participating in the 3D NAND market. Most other suppliers were supposed to ship 3D NAND devices in volumes last year, but vendors pushed out their production dates for various business and technical reasons.
Going into 2015,
Samsung continues to expand its 3D NAND production. In addition, Micron and its 3D NAND partner,
Intel, have recently begun sampling 3D NAND chips, with production slated for the second half of 2015. Another 3D NAND vendor, SK Hynix, plans to move into pilot production later this year.
As previously stated, the SanDisk/Toshiba duo won’t ship 3D NAND until 2016. Meanwhile, Spansion and China’s XMC recently announced a joint agreement to make 3D NAND, with production slated for 2017.
Still, 3D NAND isn’t expected to move into mainstream production until 2017, which is a year or two later than expected. 3D NAND is the eventual successor to today’s 2D NAND, but 3D NAND is more difficult to make than previously thought. 3D NAND resembles a skyscraper, in which horizontal levels are stacked and then connected using tiny vertical channels.
“(3D NAND) will start to ramp in 2016, but it’s a new technology and it will take time to qualify in applications,” said Greg Wong, an analyst with Forward Insights. “It will gain steam in 2017.”
Still, OEMs want to get their hands on 3D NAND sooner than later. So, 3D NAND customers may be asking themselves some simple questions—What are the challenges? And what will it take to get the technology over the hump?
As it turns out, there are a number of challenges on the manufacturing front. In no particular order, alternating stack deposition, metal deposition, high-aspect-ratio etch and metrology are arguably the most difficult process steps for 3D NAND. “Above all, metrology was the most underestimated and under-invested for the industry’s readiness for vertical NAND,” said Naga Chandrasekaran, vice president of process R&D at Micron Technology. “We have these vertical structures and recessed structures within these vertical spaces, but we cannot measure them today.”
Why 3D NAND?
For the foreseeable future, today’s 2D NAND will remain the mainstream technology due to costs. In 2D NAND, the transistor has two gates. The control gate is on the top of the device. The floating gate is in the middle, which is surrounded by a dielectric.
Thanks to 193nm immersion and self-aligned double/quadruple patterning, vendors have extended planar NAND down to the 1xnm node. But at that node, vendors are struggling to scale the floating gate. “In fact, the floating gate is seeing an undesirable reduction in the capacitive coupling to the control gate,” said Jim Handy, an analyst with Objective Analysis.
2D NAND will run out of steam at 10nm, prompting the need for 3D NAND. Unlike planar NAND, 3D NAND makes use of vertical stacks or layers to increase the densities.
Today, the big market for 3D NAND is solid-state drives (SSDs) for niche-oriented enterprise applications. But as 3D NAND becomes more cost competitive, the devices are moving beyond the enterprise. “We (will bolster) our product competitiveness by expanding V-NAND in all segments of SSDs,” said Ji Ho Pak, vice president of memory marketing at Samsung Electronics, in a recent conference call.
Samsung refers to its 3D NAND technology as V-NAND. So far, the company has introduced two V-NAND devices, including 24- and 32-layer chips, based on 30nm to 40nm design rules.
But even at 32 layers, 3D NAND still does not reach cost parity with 2D NAND, keeping 3D NAND at a price premium. In 2015, though, vendors are expected to ship 40- and 48-layer devices, which will bring 3D NAND closer to the price-per-bit curve with 2D NAND.
“It’s a moving target where the true crossover is in terms of the cost-per-bit,” said Bradley Howard, vice president of the Etch Advanced Technology unit at
Applied Materials. “The crossover will probably occur closer to 40 to 48 device stacks, as opposed to the 24 and 32 device stacks you are seeing now.”
Howard is also seeing a big shift in the 3D NAND ramp. “We can see the wave building up over the course of this year, based on the interest in tool buys and product ramps,” he said. “And you will see the big ramps going on probably at the end of this year and into 2016.”
At the end of 2014, there were a total of 60,000 to 65,000 wafers starts per month (wspm) in terms of installed capacity for 3D NAND, said Martin Anstice, president and chief executive of Lam Research, in a recent conference call.
Of that figure, Samsung had around 40,000 wspm of installed capacity, according to Pacific Crest Securities. By the end of 2015, the industry is projected to have a total of 130,000 wspm (plus or minus 10,000) of 3D NAND capacity installed, Lam’s Anstice said.
The new litho: alternating stack deposition
Still, there are some big challenges. To make the technology more cost competitive, vendors must scale 3D NAND well beyond 48 layers. In fact, the number of layers is not determined by traditional lithography. Planar NAND requires advanced lithography, while 3D NAND does not. Because the current 3D NAND devices make use of trailing-edge design rules, the challenges shift from lithography to deposition and etch.
The 3D NAND flow starts with a substrate. Then, vendors undergo the first major challenge in the flow—alternating stack deposition. Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer on the substrate.
This process is much like making a layer cake. As a chipmaker adds more layers, the device becomes more complex. “Obviously, with these multiple layers, uniformity, repeatability and low defects are becoming critical,” Applied Howard’s said.
There are other issues. “Those alternating layers require a very precise thickness. They require film and surface integrity between each of the layers. And you have to do that in a cost effective way. If I’m putting down 32, 40 and 64 layers, you don’t want it to take forever,” said Dave Hemker, senior vice president and chief technology officer at
Lam Research. “There is also a stress concern. As you put down dielectric films, they could have varying degrees of tensile or compressive stress. With a couple of layers, it’s not really something to worry about. But when you start stacking so many of these layers on top of each other, you can run into problems.”
High-aspect ratio etch
Following that step, a hard mask is applied on the surface and holes are patterned on the top. Then, here comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate.
“It’s not just the aspect ratios, but it’s also how deep we have to go,” Applied’s Howard said. “If you take typical planar NAND, you are looking at 12:1 or 15:1 contacts. In 3D NAND, you are looking at 40:1 to 60:1 high-aspect ratios.”
To illustrate the complexity, Samsung’s initial 24-layer device has 2.5 million tiny trenches or channels in the same chip. Each of them must be parallel and uniform. “You need to have perfectly vertical profiles and they need to maintain the CD,” added Lam’s Hemker.
Metal deposition
After the trenches are formed, the device requires contacts. The device is backfilled with a conductor using a metal deposition step.
“There is a challenge in the metal deposition area,” Hemker said. “Typically, in one of the flows, they will wet etch out a nitride layer and backfill it. We’re seeing a lot of customers’ backfilling it with tungsten. And that’s a tricky deposition, because you are doing a non-line of sight deposition. So you basically have these caves and tunnels in there. You have to go back in there after the fact and put in tungsten metal. If you don’t engineer the process right, you may put in this pre-cursor that wants to plate out metallic tungsten. Given its own way, it could plate out right when it gets into the hole. So you have a lot of ways to create voids.”
Metrology
At various steps, the structure goes through a rigorous metrology and inspection flow. The workhorse metrology tool is the scanning electron microscope, which measures the critical dimensions in chips. Another technology, optical scatterometry, analyzes changes in the intensity of light.
One of the many challenges is to find a defect in a multi-layer 3D NAND stack and determine its exact location. “If you look at a planar device, you can look at the top down and get a feel for what’s going on,” Applied’s Howard said. “In these 3D structures, you start getting into 32 or 48 layers. If there’s something going on somewhere in the middle of that stack, your ability to see it is a challenge.”
The big problem is that the current metrology tools are falling short. “The vertical NAND industry is moving very fast, but the characterization requirements of vertical NAND are significant and we don’t have the right techniques in place,” Micron’s Chandrasekaran said.
3D NAND vendors can use the existing metrology tools, at least to some degree. “The tool says there is a defect, but I can’t see it,” Chandrasekaran said. “You have to do a cross section, and you need to find the defect. Then you wait for an electrical signature. That’s too long.”
The metrology tools are making progress, although somewhat more slowly than the industry wants. “It’s taking the traditional methodology and trying to get a better understanding of the data coming off of it,” Applied’s Howard said. “For example, if you are putting an e-beam on a surface, you are getting electron beams on and secondary electrons are coming off. How to interpret that signal gives you the information. There is a lot of work going in how to interpret the signals. As we get more and more data coming out, the ability to build the right algorithms for interpreting the data will mature over time.”
Still, there is room for innovation in the arena. “Everyone knew inspection would be difficult. But it turned out to be very difficult. That’s one of the areas where there is a lot of opportunity for improvement,” he said.
