3D NAND Manufacturing Issues

Currently the 3D manufacturing process is being developed to manufacture NAND flash (see the article below). However, it would be very useful to use for other product technologies such as DRAM, logic and analog. For logic products the process development emphasis would be on increasing the number of metal levels and their connections to vertical transistors. For DRAM products the  emphasis would be on adding memory cells that are located in layers vertically above the silicon substrate surface.

The article below discusses processing issues such as

"the challenges here are focused on variability control of several key processes....Alternating stack deposition must have precise control with good uniformities and low defectivity. “Initially, the uniformities must be good,” Applied’s Ping said. “It’s all going back to stress control because the alternating films are different. For each film there could be a mismatch. Stress could show up.”

“Repeatability at every single step is also critical and it has to be done at high productivity in order to keep costs down,”

"Tiny trenches or channels are etched from the top of the device to the substrate. To illustrate the complexity of this step, Samsung’s 3D NAND device has 2.5 million tiny channels in the same chip. Each of them must be parallel and uniform.”

One area that the article does not mentions is the additional circuitry complication of the 3D NAND products. For example there is a need to sense correctly and repeatedly every one of the larger number of smaller memory cells that are on each 3D NAND. Also the controller of the 3D NAND has to deal with the larger number of memory cells that need to be accessed and controlled. 

Ron

Insightful, timely, and accurate semiconductor consulting.

Semiconductor information and news at - http://www.maltiel-consulting.com/

How To Make 3D NAND

Foundries progress with complex combination of high-aspect ratio etch, metal deposition and string stacking.

MAY 23RD, 2016 - BY: MARK LAPEDUS

In 2013, Samsung reached a major milestone in the IC industry by shipping the world’s first 3D NAND device. Now, after some delays and uncertainty, Intel, Micron, SK Hynix and the SanDisk/Toshiba duo are finally ramping up or sampling 3D NAND.

3D NAND is the long-awaited successor to today’s planar or 2D NAND, which is used in memory cards, solid-state storage drives (SSDs), USB flash drives and other products.

There is still huge demand for today’s planar NAND, but this technology is basically reaching its physical scaling limit. Today, NAND flash vendors are shipping planar parts at the mid-1xnm node regime, which represents the end of the scaling road for the technology.

So to extend NAND, OEMs want 3D NAND. 3D NAND is shipping, but the technology isn’t expected to hit the mainstream until 2017, which is one to two years longer than expected.

3D NAND is more difficult to make than previously thought. Unlike 2D NAND, which is a planar structure, 3D NAND resembles a vertical skyscraper. A 3D NAND device consists of multiple levels or layers, which are stacked and then connected using tiny vertical channels.

Today’s leading-edge 3D NAND parts are 32- and 48-layer devices. Scaling 3D NAND to 64 layers and beyond presents some major challenges. And in fact, today’s 3D NAND is expected to hit the ceiling at or near 128 layers.

“This is the limitation,” said Er-Xuan Ping, managing director of memory and materials within the Silicon Systems Group at Applied Materials. “Up to a certain point, a single-string is limited by etching or other process steps.”

So to extend 3D NAND beyond 128 layers, the industry is quietly developing a technology called string stacking. Still in R&D, string stacking involves a process of stacking individual 3D NAND devices on top of each other. For example, if one stacks three 64-layer 3D NAND devices on top of each other, the resulting chip would represent a 192-layer product. The trick is to link the individual 64-layer devices with some type of interconnect scheme.

String stacking is already in the works. For example, Micron Technology, according to multiple sources, recently demonstrated a 64-layer 3D NAND device by stringing two 32-layer chips together.

This is not a simple technology to develop, however. And even with string stacking, 3D NAND would top out at or around 300 layers, according to experts.

All told, 3D NAND is projected to remain viable at least until 2020 and perhaps beyond. “This is a 10-plus year roadmap and we are just at the beginning of it,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research.

In any case, OEMs will need to get a handle on the 3D NAND manufacturing issues in order to have more realistic expectations about their design schedules. To help OEMs, Semiconductor Engineering has taken a look at some of the more challenging process steps for 3D NAND. This includes alternating step deposition, high aspect ratio etch, metal deposition and string stacking.

Why 3D NAND?
In today systems, the memory hierarchy is fairly straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. And disk drives and NAND-based SSDs are used for storage.

NAND, a nonvolatile memory technology, is based on the traditional floating gate transistor structure. Thanks to 193nm immersion lithography and multiple patterning, vendors have extended planar NAND down to the 1xnm node regime.

But at 1xnm, there are issues cropping up. “In fact, the floating gate is seeing an undesirable reduction in the capacitive coupling to the control gate,” said Jim Handy, an analyst with Objective Analysis.

So, today’s planar NAND will soon stop scaling, prompting the need for 3D NAND. Basically, 3D NAND resembles a vertical skyscraper or layer cake. The layers, which are horizontal, are the active wordlines. “The bitlines also run horizontally in the metal layers on the top of the chip,” Handy said. “The vertical channels are the NAND ‘strings’ that attach to the bitlines.”

Meanwhile, vendors are at various stages of ramping up the technology. Samsung, the leader in 3D NAND, last year shipped its third-generation 3D NAND device—a 48-layer chip. In addition, Micron and its 3D NAND partner, Intel, have recently begun shipping their first 3D NAND chip—a 32-layer device. Both SK Hynix and the SanDisk/Toshiba duo are separately sampling 48-layer chips.

2016 is expected to be a big year for 3D NAND. At the end of 2015, there was a total of 160,000 wafer starts per month (wspm) in terms of worldwide installed capacity for 3D NAND, according to Lam Research. “We estimate that the industry will ship approximately 350,000 to 400,000 wspm of 3D NAND capable capacity by the end of 2016,” Lam’s Pan said.

Still, 3D NAND represents a fraction of the total installed capacity for NAND (2D and 3D), which is roughly 1.3 million to 1.4 million wspm. “Eventually, we expect a significant majority of the NAND installed base to become 3D capable,” Pan said.

Vendors are ramping up these devices in new or converted 3D NAND fabs. In total, the equipment cost for a 2D NAND fab ranges from $30 million to $45 million for 1,000 wspm, according to Christian Dieseldorff, an analyst with the Industry Research & Statistics group at SEMI.

In comparison, the equipment cost for a 3D NAND fab ranges from $50 million to $65 million for 1,000 wspm, Dieseldorff said. “3D NAND equipment costs are higher because more equipment like CVD and etch tools are needed,” he said.

Some vendors are retrofitting their current fabs into 3D NAND facilities. “We expect 2X to 4X more space is needed when converting from 2D to 3D. In this case, there is a high degree of re-use because most equipment is already there. Again, additional CVD and etch tools are needed,” he said.

Still, a 3D NAND fab is not as expensive as a leading-edge logic fab. A 7nm logic processes, for example, will require a $160 million fab equipment investment for every 1,000 wspm, according to Gartner.

The new litho: alternating stack deposition 
In any case, 3D NAND represents a major departure from today’s planar NAND. In 2D NAND, the fabrication process is dependent on advanced lithography. In 3D NAND, though, vendors are using trailing-edge 40nm to 20nm design rules. Lithography is still used, but it isn’t the most critical step. So for 3D NAND, the challenges shift from lithography to deposition and etch.

In fact, 3D NAND introduces a number of new and difficult process steps to the semiconductor industry. “By moving the bit-string into the third-dimension, this technology eases many of the patterning-scaling challenges,” said David Fried, chief technology officer at Coventor. “But it has introduced several fairly complex and new processes. Uniformity of these processes is critical. So, from my perspective, the challenges here are focused on variability control of several key processes.”

The 3D NAND flow starts with a substrate. Then, vendors undergo the first major challenge in the flow—alternating stack deposition. Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer on the substrate.

This process is much like making a layer cake. In simple terms, a layer of material is deposited on the substrate. Then, another layer of material is deposited on top of that. The process is repeated several times until a given device has the desired number of layers.

Each vendor uses a different set of materials to create a stack of layers. For example, to make its 3D NAND devices, Samsung deposits alternating layers of silicon nitride and silicon dioxide on the substrate, according to Objective Analysis. In contrast, Toshiba’s 3D NAND technology consists of alternating layers of conductive polysilicon and insulating silicon dioxide, according to the firm.

Alternating stack deposition must have precise control with good uniformities and low defectivity. “Initially, the uniformities must be good,” Applied’s Ping said. “It’s all going back to stress control because the alternating films are different. For each film there could be a mismatch. Stress could show up.”

The challenges escalate as vendors increase the number of layers in a device. “Repeatability at every single step is also critical and it has to be done at high productivity in order to keep costs down,” Lam’s Pan said.

High aspect ratio etch
Following the alternating stack deposition step, a hard mask is applied on the surface and holes are patterned on the top. Then, here comes the hardest part of the flow—high-aspect ratio etch.

Tiny trenches or channels are etched from the top of the device to the substrate. To illustrate the complexity of this step, Samsung’s 3D NAND device has 2.5 million tiny channels in the same chip. Each of them must be parallel and uniform.

Today’s high-aspect ratio etch tools can handle the requirements for 32- and 48-layer devices. For these chips, the aspect ratios range from 30:1 to 40:1. “This etch is really complex. Uniformity is absolutely critical to the performance of the memory device,” Coventor’s Fried said. “The statistics are also staggering. Once the etch is complete, the amount of processing that takes place inside that hole is also pretty impressive.”

The problem? Current high aspect ratio etch tools are either not ready or struggling to meet the demands for 64-layer devices and beyond. At 64 layers, the aspect ratios are 60:1 to 70:1. “This is too high for current etching capability,” Applied’s Ping said. “The etching and hard mask technologies are not necessarily available for 60:1 or 70:1.”

So going forward, NAND vendors are simultaneously following two paths. First, they will wait for the next-generation high-aspect ratio etch tools and other technologies to arrive. And then, provided the etchers are ready on time, they may scale today’s 3D NAND in the following progressions—32 and 48 layers, to 64 layers, to 96, and then to 128.

In the second path, NAND vendors also will develop next-generation string stacking technology (see below for details).

Charge trap versus floating gate 
Before moving to string stacking, vendors will continue to scale today’s 3D NAND. Besides deposition and etch, today’s 3D NAND undergoes other complex steps, including the formation of the gate.

For this, the industry is moving in two directions. Samsung, SK Hynix and the SanDisk/Toshiba duo are making use of charge trap flash technology. This technology uses a non-conductive layer of silicon nitride. The layer wraps around the control gate of a cell, which, in turn, traps electrical charges to maintain cell integrity.

In contrast, the Intel/Micron duo are not using charge trap. Instead, they have extended the floating gate structure to 3D NAND. “In floating gate, the gate is actually a conductor,” Objective Analysis’ Handy said. “A charge trap layer, which actually looks like a floating gate, is an insulator.”

Floating gate involves some difficult patterning steps. “It’s hard to pattern things on the sides of a vertical hole that you’ve made. You have to go through a lot of process steps,” Handy said.

Charge trap also has some drawbacks. “The advantage with charge trap is that you don’t have to pattern it. Charge trap is easier to make that way,” he said. “Excluding Spansion, which ships over 80% of all bytes in charge trap, nobody else has been able to make charge trap cost effectively.”

Metal deposition
Once the gate is developed, the next step is difficult. The device requires contacts. The device is backfilled with a conductor using a metal deposition step.

“There is a challenge in the metal deposition area,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “We’re seeing a lot of customers’ backfilling it with tungsten. And that’s a tricky deposition, because you are doing a non-line-of-sight deposition. So you basically have these caves and tunnels in there. You have to go back in there after the fact and put in tungsten metal. If you don’t engineer the process right, you may put in this pre-cursor that wants to plate out metallic tungsten. Given its own way, it could plate out right when it gets into the hole. So you have a lot of ways to create voids.”

String stacking
There are other difficult steps in the flow, but the biggest challenge is clear. Until the industry solves the high aspect ratio etch issues, today’s single-string 3D NAND technology is arguably stuck at 48 and/or 64 layers.

And even when the etchers are ready, today’s single-string 3D NAND hits the wall at 128 layers. “This is because the aspect ratio is limited by the process,” Applied’s Ping said. “So you must figure out a way to bypass the limitations.”

So what’s the answer? String stacking. In this approach, vendors will stack individual 3D NAND devices. Each device might be separated by an insulating layer. “When you do string stacking, you finish one string,” Ping said. “Then, you are repeating the steps. It’s difficult, but you can do it.”

For example, a vendor will develop a 48-layer device. To devise that chip, it will go through the same process flow, such as alternating layer deposition, etch and others.

Then, the vendor will develop a separate 48-layer chip using the same flow. The process is not limited to 48-layer chips. A vendor could also stack multiple 32-layer chips. And if the technology is available, a vendor could stack 64-, 96- and perhaps 128-layer devices.

In theory, though, vendors may opt for string stacking with 32- and 48-layer chips. There is less stress for an individual 32- or 48-layer device, as compared to a 96- or 128-layer chip.

Ultimately, though, 3D NAND with string stacking may run out of steam at or near 300 layers. “It will hit a problem in terms of yield,” Ping said. “When you stack, the yield loss from defects continues building up. That will be the limitation. Plus, everything will be limited by stress. If you put too much film, then the stress presents a limitation.”

Still to be seen, however, is how vendors will connect the individual 3D NAND devices together in string stack. For this, the industry is looking at various interconnect schemes. “There will be four or five different options,” he said. “You can build a shared bit line in the middle. Then, another option is that you build a string, which contacts each string directly.”

To be sure, though, there are still many unknowns and challenges with string stacking. The industry also faces several challenges even without string stacking. In either case, the industry must continue to master and perfect the various process steps with 3D NAND. Otherwise, the technology will remain costly, at least for the vast majority of OEMs.

Semiconductor Fabrication Growth for 2016 and 2017

Estimates by SEMI.org for 2016 and 2017 fab growth are in the article below. 

However Intel/ Micron's XPoint memory introduction in 2016 and developments of other type of 3D processing will impact fab lines capacity and the growth of semiconductor processing equipment.

Some key points from the article:

"Fab equipment spending- ....activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to $36 billion in 2016, 1.5% over 2015, and to $40.7 billion in 2017, up 13%."

"leading-edge technologies...also in 3D technologies....more conversions of older fabs may take place, but also additional new fabs and lines may begin construction."

3D process demand for etch and deposition is already impacting Applied Materials; see their recent quarterly results - Orders for the second quarter were $3.45 billion, up 37% from ayear earlier

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

SEMIforecasts 19 new fabs and lines for 2016/7

By David Manners  10th June 2016

Nineteen new fabs and lines are forecasted to begin construction in 2016 and 2017, according to SEMI.

While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5% growth over 2015 is expected while 13% growth is forecast in 2017.

Fab equipment spending – including new, secondary, and in-house – was down 2% in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to $36 billion in 2016, 1.5% over 2015, and to $40.7 billion in 2017, up 13%.

Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60% or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year.

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

Process Challenges of 3D (Vertical Transistors)

The article below describes the drive toward 3D vertical transistors above the surface of the chip's die.

"3D NAND represents a major departure from today’s planar NAND. In 2D NAND, the fabrication process is dependent on advanced lithography. In 3D NAND, though, vendors are using trailing-edge 40nm to 20nm design rules. Lithography is still used, but it isn’t the most critical step. So for 3D NAND, the challenges shift from lithography to deposition and etch.”

However the new 3D processes are not easy to implement.

"3D NAND introduces a number of new and difficult process steps to the semiconductor industry...."it has introduced several fairly complex and new processes. Uniformity of these processes is critical. So, from my perspective, the challenges here are focused on variability control of several key processes.”

It will be interesting how well Intel and Micron XPoint (see SSD, 3D Vertical NAND, or 3D XPoint?) products will succeed against current 3D products (see November 2012 3D NAND flash is coming)

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

How To Make 3D NAND

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Foundries progress with complex combination of high-aspect ratio etch, metal deposition and string stacking.

MAY 23RD, 2016 - BY: MARK LAPEDUS

In 2013, Samsung reached a major milestone in the IC industry by shipping the world’s first 3D NAND device. Now, after some delays and uncertainty, Intel, Micron, SK Hynix and the SanDisk/Toshiba duo are finally ramping up or sampling 3D NAND.

3D NAND is the long-awaited successor to today’s planar or 2D NAND, which is used in memory cards, solid-state storage drives (SSDs), USB flash drives and other products.

There is still huge demand for today’s planar NAND, but this technology is basically reaching its physical scaling limit. Today, NAND flash vendors are shipping planar parts at the mid-1xnm node regime, which represents the end of the scaling road for the technology.

So to extend NAND, OEMs want 3D NAND. 3D NAND is shipping, but the technology isn’t expected to hit the mainstream until 2017, which is one to two years longer than expected.

3D NAND is more difficult to make than previously thought. Unlike 2D NAND, which is a planar structure, 3D NAND resembles a vertical skyscraper. A 3D NAND device consists of multiple levels or layers, which are stacked and then connected using tiny vertical channels.

Today’s leading-edge 3D NAND parts are 32- and 48-layer devices. Scaling 3D NAND to 64 layers and beyond presents some major challenges. And in fact, today’s 3D NAND is expected to hit the ceiling at or near 128 layers.

“This is the limitation,” said Er-Xuan Ping, managing director of memory and materials within the Silicon Systems Group at Applied Materials. “Up to a certain point, a single-string is limited by etching or other process steps.”

So to extend 3D NAND beyond 128 layers, the industry is quietly developing a technology called string stacking. Still in R&D, string stacking involves a process of stacking individual 3D NAND devices on top of each other. For example, if one stacks three 64-layer 3D NAND devices on top of each other, the resulting chip would represent a 192-layer product. The trick is to link the individual 64-layer devices with some type of interconnect scheme.

String stacking is already in the works. For example, Micron Technology, according to multiple sources, recently demonstrated a 64-layer 3D NAND device by stringing two 32-layer chips together.

This is not a simple technology to develop, however. And even with string stacking, 3D NAND would top out at or around 300 layers, according to experts.

All told, 3D NAND is projected to remain viable at least until 2020 and perhaps beyond. “This is a 10-plus year roadmap and we are just at the beginning of it,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research.

In any case, OEMs will need to get a handle on the 3D NAND manufacturing issues in order to have more realistic expectations about their design schedules. To help OEMs, Semiconductor Engineering has taken a look at some of the more challenging process steps for 3D NAND. This includes alternating step deposition, high aspect ratio etch, metal deposition and string stacking.

Why 3D NAND?
In today systems, the memory hierarchy is fairly straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. And disk drives and NAND-based SSDs are used for storage.

NAND, a nonvolatile memory technology, is based on the traditional floating gate transistor structure. Thanks to 193nm immersion lithography and multiple patterning, vendors have extended planar NAND down to the 1xnm node regime.

But at 1xnm, there are issues cropping up. “In fact, the floating gate is seeing an undesirable reduction in the capacitive coupling to the control gate,” said Jim Handy, an analyst with Objective Analysis.

So, today’s planar NAND will soon stop scaling, prompting the need for 3D NAND. Basically, 3D NAND resembles a vertical skyscraper or layer cake. The layers, which are horizontal, are the active wordlines. “The bitlines also run horizontally in the metal layers on the top of the chip,” Handy said. “The vertical channels are the NAND ‘strings’ that attach to the bitlines.”

Meanwhile, vendors are at various stages of ramping up the technology. Samsung, the leader in 3D NAND, last year shipped its third-generation 3D NAND device—a 48-layer chip. In addition, Micron and its 3D NAND partner, Intel, have recently begun shipping their first 3D NAND chip—a 32-layer device. Both SK Hynix and the SanDisk/Toshiba duo are separately sampling 48-layer chips.

2016 is expected to be a big year for 3D NAND. At the end of 2015, there was a total of 160,000 wafer starts per month (wspm) in terms of worldwide installed capacity for 3D NAND, according to Lam Research. “We estimate that the industry will ship approximately 350,000 to 400,000 wspm of 3D NAND capable capacity by the end of 2016,” Lam’s Pan said.

Still, 3D NAND represents a fraction of the total installed capacity for NAND (2D and 3D), which is roughly 1.3 million to 1.4 million wspm. “Eventually, we expect a significant majority of the NAND installed base to become 3D capable,” Pan said.

Vendors are ramping up these devices in new or converted 3D NAND fabs. In total, the equipment cost for a 2D NAND fab ranges from $30 million to $45 million for 1,000 wspm, according to Christian Dieseldorff, an analyst with the Industry Research & Statistics group at SEMI.

In comparison, the equipment cost for a 3D NAND fab ranges from $50 million to $65 million for 1,000 wspm, Dieseldorff said. “3D NAND equipment costs are higher because more equipment like CVD and etch tools are needed,” he said.

Some vendors are retrofitting their current fabs into 3D NAND facilities. “We expect 2X to 4X more space is needed when converting from 2D to 3D. In this case, there is a high degree of re-use because most equipment is already there. Again, additional CVD and etch tools are needed,” he said.

Still, a 3D NAND fab is not as expensive as a leading-edge logic fab. A 7nm logic processes, for example, will require a $160 million fab equipment investment for every 1,000 wspm, according to Gartner.

The new litho: alternating stack deposition 
In any case, 3D NAND represents a major departure from today’s planar NAND. In 2D NAND, the fabrication process is dependent on advanced lithography. In 3D NAND, though, vendors are using trailing-edge 40nm to 20nm design rules. Lithography is still used, but it isn’t the most critical step. So for 3D NAND, the challenges shift from lithography to deposition and etch.

In fact, 3D NAND introduces a number of new and difficult process steps to the semiconductor industry. “By moving the bit-string into the third-dimension, this technology eases many of the patterning-scaling challenges,” said David Fried, chief technology officer at Coventor. “But it has introduced several fairly complex and new processes. Uniformity of these processes is critical. So, from my perspective, the challenges here are focused on variability control of several key processes.”

The 3D NAND flow starts with a substrate. Then, vendors undergo the first major challenge in the flow—alternating stack deposition. Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer on the substrate.

This process is much like making a layer cake. In simple terms, a layer of material is deposited on the substrate. Then, another layer of material is deposited on top of that. The process is repeated several times until a given device has the desired number of layers.

Each vendor uses a different set of materials to create a stack of layers. For example, to make its 3D NAND devices, Samsung deposits alternating layers of silicon nitride and silicon dioxide on the substrate, according to Objective Analysis. In contrast, Toshiba’s 3D NAND technology consists of alternating layers of conductive polysilicon and insulating silicon dioxide, according to the firm.

Alternating stack deposition must have precise control with good uniformities and low defectivity. “Initially, the uniformities must be good,” Applied’s Ping said. “It’s all going back to stress control because the alternating films are different. For each film there could be a mismatch. Stress could show up.”

The challenges escalate as vendors increase the number of layers in a device. “Repeatability at every single step is also critical and it has to be done at high productivity in order to keep costs down,” Lam’s Pan said.

High aspect ratio etch
Following the alternating stack deposition step, a hard mask is applied on the surface and holes are patterned on the top. Then, here comes the hardest part of the flow—high-aspect ratio etch.

Tiny trenches or channels are etched from the top of the device to the substrate. To illustrate the complexity of this step, Samsung’s 3D NAND device has 2.5 million tiny channels in the same chip. Each of them must be parallel and uniform.

Today’s high-aspect ratio etch tools can handle the requirements for 32- and 48-layer devices. For these chips, the aspect ratios range from 30:1 to 40:1. “This etch is really complex. Uniformity is absolutely critical to the performance of the memory device,” Coventor’s Fried said. “The statistics are also staggering. Once the etch is complete, the amount of processing that takes place inside that hole is also pretty impressive.”

The problem? Current high aspect ratio etch tools are either not ready or struggling to meet the demands for 64-layer devices and beyond. At 64 layers, the aspect ratios are 60:1 to 70:1. “This is too high for current etching capability,” Applied’s Ping said. “The etching and hard mask technologies are not necessarily available for 60:1 or 70:1.”

So going forward, NAND vendors are simultaneously following two paths. First, they will wait for the next-generation high-aspect ratio etch tools and other technologies to arrive. And then, provided the etchers are ready on time, they may scale today’s 3D NAND in the following progressions—32 and 48 layers, to 64 layers, to 96, and then to 128.

In the second path, NAND vendors also will develop next-generation string stacking technology (see below for details).

Charge trap versus floating gate 
Before moving to string stacking, vendors will continue to scale today’s 3D NAND. Besides deposition and etch, today’s 3D NAND undergoes other complex steps, including the formation of the gate.

For this, the industry is moving in two directions. Samsung, SK Hynix and the SanDisk/Toshiba duo are making use of charge trap flash technology. This technology uses a non-conductive layer of silicon nitride. The layer wraps around the control gate of a cell, which, in turn, traps electrical charges to maintain cell integrity.

In contrast, the Intel/Micron duo are not using charge trap. Instead, they have extended the floating gate structure to 3D NAND. “In floating gate, the gate is actually a conductor,” Objective Analysis’ Handy said. “A charge trap layer, which actually looks like a floating gate, is an insulator.”

Floating gate involves some difficult patterning steps. “It’s hard to pattern things on the sides of a vertical hole that you’ve made. You have to go through a lot of process steps,” Handy said.

Charge trap also has some drawbacks. “The advantage with charge trap is that you don’t have to pattern it. Charge trap is easier to make that way,” he said. “Excluding Spansion, which ships over 80% of all bytes in charge trap, nobody else has been able to make charge trap cost effectively.”

Metal deposition
Once the gate is developed, the next step is difficult. The device requires contacts. The device is backfilled with a conductor using a metal deposition step.

“There is a challenge in the metal deposition area,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “We’re seeing a lot of customers’ backfilling it with tungsten. And that’s a tricky deposition, because you are doing a non-line-of-sight deposition. So you basically have these caves and tunnels in there. You have to go back in there after the fact and put in tungsten metal. If you don’t engineer the process right, you may put in this pre-cursor that wants to plate out metallic tungsten. Given its own way, it could plate out right when it gets into the hole. So you have a lot of ways to create voids.”

String stacking
There are other difficult steps in the flow, but the biggest challenge is clear. Until the industry solves the high aspect ratio etch issues, today’s single-string 3D NAND technology is arguably stuck at 48 and/or 64 layers.

And even when the etchers are ready, today’s single-string 3D NAND hits the wall at 128 layers. “This is because the aspect ratio is limited by the process,” Applied’s Ping said. “So you must figure out a way to bypass the limitations.”

So what’s the answer? String stacking. In this approach, vendors will stack individual 3D NAND devices. Each device might be separated by an insulating layer. “When you do string stacking, you finish one string,” Ping said. “Then, you are repeating the steps. It’s difficult, but you can do it.”

For example, a vendor will develop a 48-layer device. To devise that chip, it will go through the same process flow, such as alternating layer deposition, etch and others.

Then, the vendor will develop a separate 48-layer chip using the same flow. The process is not limited to 48-layer chips. A vendor could also stack multiple 32-layer chips. And if the technology is available, a vendor could stack 64-, 96- and perhaps 128-layer devices.

In theory, though, vendors may opt for string stacking with 32- and 48-layer chips. There is less stress for an individual 32- or 48-layer device, as compared to a 96- or 128-layer chip.

Ultimately, though, 3D NAND with string stacking may run out of steam at or near 300 layers. “It will hit a problem in terms of yield,” Ping said. “When you stack, the yield loss from defects continues building up. That will be the limitation. Plus, everything will be limited by stress. If you put too much film, then the stress presents a limitation.”

Still to be seen, however, is how vendors will connect the individual 3D NAND devices together in string stack. For this, the industry is looking at various interconnect schemes. “There will be four or five different options,” he said. “You can build a shared bit line in the middle. Then, another option is that you build a string, which contacts each string directly.”

To be sure, though, there are still many unknowns and challenges with string stacking. The industry also faces several challenges even without string stacking. In either case, the industry must continue to master and perfect the various process steps with 3D NAND. Otherwise, the technology will remain costly, at least for the vast majority of OEMs.

3D Semi. Manufacturing Will Benefit LAM, Applied and Other Semiconductor Equipment Vendors

3D semiconductor chip process demand will have a very large impact on semiconductor equipment vendors over the next several years. Initially it is being implemented only on NAND flash

3D chip manufacturing will be implemented by many other types of semiconductor chips such as DRAM memories and other high density ICs.

Historically chip size has been shrinking by using stringent photolithography processes. 3D chip manufacturing enables shrinking chip size while using more relaxed photolithography processes,

3D chip manufacturing relaxes photolithography, but it adds stringent demands on other semiconductor manufacturing processes such as layers deposition and etch. This will increase the demand for equipment vendors such as Applied Materials and LAM as is discussed in the article below.

More about 3D semiconductor from November 2012 is in-  3D NAND flash is coming

More about the processing difficulties is in Applied Materials talks about 3D NAND flash production .

A 2009 patent application by Samsung for this technology is - US20100155810

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Lam, Applied to Ride Price Decline of 3-D NAND, Says Credit Suisse

By Tiernan Ray

Credit Suisse’s chip equipment analyst Farhan Ahmad and chip analyst John Pitzer today write that equipment vendors Lam Research (LRCX) and Applied Materials (AMAT) could both see multiplication of their sales as a result of newer three-dimensional NAND flash memory chips, known as “3-D NAND,” that are becoming more prevalent.

Why are the chips important? 3-D NAND chips have 35% more bits per square millimeter, the authors write, at least in the parts produced by Samsung Electronics (005930KS). With increasing “layers,” that can rise to more than double and perhaps triple the bit density.

As a result of density rising faster than costs, “As the density growth is significantly higher from 2D to 3D, than the CapEx increase from 15nm to 3D, we believe that 3D NAND roadmap can potentially provide a 20%/yr cost reductions for next two years.”

While 3-D NAND has been talked about for some time, the key is that the prices of the products are declining rapidly in the marketplace, as evidenced by Samsung’ ssolid-state drives using the chips, the authors write:

We would note the following recent data points (i) Samsung 3D NAND SSD pricing is now at parity with Planar SSDs. Retail pricing indicates that Samsung’s 3D NAND SSDs have declined 20-25% qtd and are now on price parity with leading planar SSDs. Note that 3D NAND SSD are known to have better reliability relative to 2D NAND SSDs, which makes 3D NAND SSD as better choice at same price points. We believe that recent price reductions are a sign that Samsung is trying to accelerate the adoption of 3D NAND and this could prompt other NAND companies to accelerate adoption of 3D NAND. (ii) SanDisk and Micron 3D NAND announcements are indication that 3D NAND progress is not just limited to Samsung, and there is greater evidence that 3D NAND can significantly reduce cost on NAND (our analysis suggests that 48/64 layer 3D NAND could offer >20% cost reduction over planar). Note that once 3D NAND becomes more economical relative to planar, transition to 3D could accelerate as NAND Companies try to compete on costs. (iii) We are seeing more signs of product wins for 3D NAND. Earlier today Korea Times reported that Samsung’s 3D NAND SSD had secured design wins at GOOG and AMZN data centers. Earlier this month Korea times had also reported that Samsung’s 3D NAND had won the Apple’s MacBook business for next year.

For Lam and Applied, they write,

Our analysis suggests that 3D NAND transition could potentially increase NAND WFE to $9-12bn /year for 2016-2018 versus $5-6bn over last 2 years (assuming 40% bit growth per year). We believe that NAND revenues for LRCX could potentially increase by 3x (or $1.5 bn per year) as 3D NAND accelerates. We also expect AMAT to benefit from the 3D NAND transition but estimate that NAND revenues for ASML will decline by > 50% as litho intensive CapEx for planar NAND is replaced by non litho intensive CapEx for 3D NAND.

3D Flash NAND, SSD Challenges

The article below discusses progress in applying 3D processes in fabrication of next generation flash memory. 

Some of the key challenges in developing this technology are:

"challenges on the manufacturing front. In no particular order, alternating stack deposition, metal deposition, high-aspect-ratio etch and metrology are arguably the most difficult process steps for 3D NAND. “Above all, metrology was the most underestimated and under-invested for the industry’s readiness for vertical NAND,” said Naga Chandrasekaran, vice president of process R&D at Micron Technology. “We have these vertical structures and recessed structures within these vertical spaces, but we cannot measure them today....”

My 1990 patent ( Electrical measurements of the profile of semiconductor devices during their manufacturing process ) would help resolving the vertical Metrology difficulties.

More about the processing difficulties is in Applied Materials talks about 3D NAND flash production .

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

3D NAND Market Heats Up

Chips from Samsung, Intel, Micron being sampled, with others on the way.

FEBRUARY 19TH, 2015 - BY: MARK LAPEDUS

After some delays and uncertainty in past years, the 3D NAND market is finally heating up.

In 2013 and 2014, Samsung was the only vendor participating in the 3D NAND market. Most other suppliers were supposed to ship 3D NAND devices in volumes last year, but vendors pushed out their production dates for various business and technical reasons.

Going into 2015, Samsung continues to expand its 3D NAND production. In addition, Micron and its 3D NAND partner, Intel, have recently begun sampling 3D NAND chips, with production slated for the second half of 2015. Another 3D NAND vendor, SK Hynix, plans to move into pilot production later this year.

As previously stated, the SanDisk/Toshiba duo won’t ship 3D NAND until 2016. Meanwhile, Spansion and China’s XMC recently announced a joint agreement to make 3D NAND, with production slated for 2017.

Still, 3D NAND isn’t expected to move into mainstream production until 2017, which is a year or two later than expected. 3D NAND is the eventual successor to today’s 2D NAND, but 3D NAND is more difficult to make than previously thought. 3D NAND resembles a skyscraper, in which horizontal levels are stacked and then connected using tiny vertical channels.

“(3D NAND) will start to ramp in 2016, but it’s a new technology and it will take time to qualify in applications,” said Greg Wong, an analyst with Forward Insights. “It will gain steam in 2017.”

Still, OEMs want to get their hands on 3D NAND sooner than later. So, 3D NAND customers may be asking themselves some simple questions—What are the challenges? And what will it take to get the technology over the hump?

As it turns out, there are a number of challenges on the manufacturing front. In no particular order, alternating stack deposition, metal deposition, high-aspect-ratio etch and metrology are arguably the most difficult process steps for 3D NAND. “Above all, metrology was the most underestimated and under-invested for the industry’s readiness for vertical NAND,” said Naga Chandrasekaran, vice president of process R&D at Micron Technology. “We have these vertical structures and recessed structures within these vertical spaces, but we cannot measure them today.”

Why 3D NAND?
For the foreseeable future, today’s 2D NAND will remain the mainstream technology due to costs. In 2D NAND, the transistor has two gates. The control gate is on the top of the device. The floating gate is in the middle, which is surrounded by a dielectric.

Thanks to 193nm immersion and self-aligned double/quadruple patterning, vendors have extended planar NAND down to the 1xnm node. But at that node, vendors are struggling to scale the floating gate. “In fact, the floating gate is seeing an undesirable reduction in the capacitive coupling to the control gate,” said Jim Handy, an analyst with Objective Analysis.

2D NAND will run out of steam at 10nm, prompting the need for 3D NAND. Unlike planar NAND, 3D NAND makes use of vertical stacks or layers to increase the densities.

Today, the big market for 3D NAND is solid-state drives (SSDs) for niche-oriented enterprise applications. But as 3D NAND becomes more cost competitive, the devices are moving beyond the enterprise. “We (will bolster) our product competitiveness by expanding V-NAND in all segments of SSDs,” said Ji Ho Pak, vice president of memory marketing at Samsung Electronics, in a recent conference call.

Samsung refers to its 3D NAND technology as V-NAND. So far, the company has introduced two V-NAND devices, including 24- and 32-layer chips, based on 30nm to 40nm design rules.

But even at 32 layers, 3D NAND still does not reach cost parity with 2D NAND, keeping 3D NAND at a price premium. In 2015, though, vendors are expected to ship 40- and 48-layer devices, which will bring 3D NAND closer to the price-per-bit curve with 2D NAND.

“It’s a moving target where the true crossover is in terms of the cost-per-bit,” said Bradley Howard, vice president of the Etch Advanced Technology unit at Applied Materials. “The crossover will probably occur closer to 40 to 48 device stacks, as opposed to the 24 and 32 device stacks you are seeing now.”

Howard is also seeing a big shift in the 3D NAND ramp. “We can see the wave building up over the course of this year, based on the interest in tool buys and product ramps,” he said. “And you will see the big ramps going on probably at the end of this year and into 2016.”

At the end of 2014, there were a total of 60,000 to 65,000 wafers starts per month (wspm) in terms of installed capacity for 3D NAND, said Martin Anstice, president and chief executive of Lam Research, in a recent conference call.

Of that figure, Samsung had around 40,000 wspm of installed capacity, according to Pacific Crest Securities. By the end of 2015, the industry is projected to have a total of 130,000 wspm (plus or minus 10,000) of 3D NAND capacity installed, Lam’s Anstice said.

The new litho: alternating stack deposition
Still, there are some big challenges. To make the technology more cost competitive, vendors must scale 3D NAND well beyond 48 layers. In fact, the number of layers is not determined by traditional lithography. Planar NAND requires advanced lithography, while 3D NAND does not. Because the current 3D NAND devices make use of trailing-edge design rules, the challenges shift from lithography to deposition and etch.

The 3D NAND flow starts with a substrate. Then, vendors undergo the first major challenge in the flow—alternating stack deposition. Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer on the substrate.

This process is much like making a layer cake. As a chipmaker adds more layers, the device becomes more complex. “Obviously, with these multiple layers, uniformity, repeatability and low defects are becoming critical,” Applied Howard’s said.

There are other issues. “Those alternating layers require a very precise thickness. They require film and surface integrity between each of the layers. And you have to do that in a cost effective way. If I’m putting down 32, 40 and 64 layers, you don’t want it to take forever,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “There is also a stress concern. As you put down dielectric films, they could have varying degrees of tensile or compressive stress. With a couple of layers, it’s not really something to worry about. But when you start stacking so many of these layers on top of each other, you can run into problems.”

High-aspect ratio etch
Following that step, a hard mask is applied on the surface and holes are patterned on the top. Then, here comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate.

“It’s not just the aspect ratios, but it’s also how deep we have to go,” Applied’s Howard said. “If you take typical planar NAND, you are looking at 12:1 or 15:1 contacts. In 3D NAND, you are looking at 40:1 to 60:1 high-aspect ratios.”

To illustrate the complexity, Samsung’s initial 24-layer device has 2.5 million tiny trenches or channels in the same chip. Each of them must be parallel and uniform. “You need to have perfectly vertical profiles and they need to maintain the CD,” added Lam’s Hemker.

Metal deposition
After the trenches are formed, the device requires contacts. The device is backfilled with a conductor using a metal deposition step.

“There is a challenge in the metal deposition area,” Hemker said. “Typically, in one of the flows, they will wet etch out a nitride layer and backfill it. We’re seeing a lot of customers’ backfilling it with tungsten. And that’s a tricky deposition, because you are doing a non-line of sight deposition. So you basically have these caves and tunnels in there. You have to go back in there after the fact and put in tungsten metal. If you don’t engineer the process right, you may put in this pre-cursor that wants to plate out metallic tungsten. Given its own way, it could plate out right when it gets into the hole. So you have a lot of ways to create voids.”

Metrology
At various steps, the structure goes through a rigorous metrology and inspection flow. The workhorse metrology tool is the scanning electron microscope, which measures the critical dimensions in chips. Another technology, optical scatterometry, analyzes changes in the intensity of light.

One of the many challenges is to find a defect in a multi-layer 3D NAND stack and determine its exact location. “If you look at a planar device, you can look at the top down and get a feel for what’s going on,” Applied’s Howard said. “In these 3D structures, you start getting into 32 or 48 layers. If there’s something going on somewhere in the middle of that stack, your ability to see it is a challenge.”

The big problem is that the current metrology tools are falling short. “The vertical NAND industry is moving very fast, but the characterization requirements of vertical NAND are significant and we don’t have the right techniques in place,” Micron’s Chandrasekaran said.

3D NAND vendors can use the existing metrology tools, at least to some degree. “The tool says there is a defect, but I can’t see it,” Chandrasekaran said. “You have to do a cross section, and you need to find the defect. Then you wait for an electrical signature. That’s too long.”

The metrology tools are making progress, although somewhat more slowly than the industry wants. “It’s taking the traditional methodology and trying to get a better understanding of the data coming off of it,” Applied’s Howard said. “For example, if you are putting an e-beam on a surface, you are getting electron beams on and secondary electrons are coming off. How to interpret that signal gives you the information. There is a lot of work going in how to interpret the signals. As we get more and more data coming out, the ability to build the right algorithms for interpreting the data will mature over time.”

Still, there is room for innovation in the arena. “Everyone knew inspection would be difficult. But it turned out to be very difficult. That’s one of the areas where there is a lot of opportunity for improvement,” he said.