Semiconductor Fabrication Growth for 2016 and 2017

Estimates by SEMI.org for 2016 and 2017 fab growth are in the article below. 

However Intel/ Micron's XPoint memory introduction in 2016 and developments of other type of 3D processing will impact fab lines capacity and the growth of semiconductor processing equipment.

Some key points from the article:

"Fab equipment spending- ....activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to $36 billion in 2016, 1.5% over 2015, and to $40.7 billion in 2017, up 13%."

"leading-edge technologies...also in 3D technologies....more conversions of older fabs may take place, but also additional new fabs and lines may begin construction."

3D process demand for etch and deposition is already impacting Applied Materials; see their recent quarterly results - Orders for the second quarter were $3.45 billion, up 37% from ayear earlier

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

SEMIforecasts 19 new fabs and lines for 2016/7

By David Manners  10th June 2016

Nineteen new fabs and lines are forecasted to begin construction in 2016 and 2017, according to SEMI.

While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5% growth over 2015 is expected while 13% growth is forecast in 2017.

Fab equipment spending – including new, secondary, and in-house – was down 2% in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to $36 billion in 2016, 1.5% over 2015, and to $40.7 billion in 2017, up 13%.

Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60% or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year.

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

ISSCC 2015 -Latest Circuits Innovations

Below are some highlights from 2015 " International Solid-State CircuitsConference once again served up a smorgasbord of silicon innovations."

It is interesting that while Samsung is continuing to develop 3D devices and processing on a single chip -

"Samsung described a second generation of its 128 Gbit 3-D NAND flash, a 3-bit/cell version with 32 layers now in production on a 68.9mm² die. The Korean giant is ahead of the pack in dense flash and also is expected to beat TSMC to market with 14/16nm FinFET logic later this year, a fact that help it retain archrival Apple as a foundry customer."

ITRS and Intel focus on developing chip stacks - 

"Paolo Gargini who leads the ITRS semiconductor road map effort said chip stacks are today what high-K metal gate design was in 2007, the next big requirement for progress.

Intel fellow Mark Bohr disagreed. “We need vertical interconnects one or two orders of magnitude more dense than today’s through-silicon vias,” he said"

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

18 Views of ISSCC

Intel, Xilinx debate 3-D chip stacks

Rick Merritt  2/26/2015 10:42 AM EST 

SAN FRANCISCO — This year’s International Solid-State Circuits Conference once again served up a smorgasbord of silicon innovations. Despite the rising costs and complexity of chasing Moore’s Law, engineers cooked up smaller, faster, more media-rich devices and the strange new world of ultra-low power design delivered a few exotic dishes at the annual gathering of chip designers.
My time at the event started with a reception where for the first time I met Lynn Conway, co-author of one of the landmark texts in chip design. In 1979, Conway’s MPC79 event paved the way for quickly turning software files into running chip prototypes, establishing a model of how to spread enabling abstractions quickly to enable innovation.

Samsung described a second generation of its 128 Gbit 3-D NAND flash, a 3-bit/cell version with 32 layers now in production on a 68.9mm² die. The Korean giant is ahead of the pack in dense flash and also is expected to beat TSMC to market with 14/16nm FinFET logic later this year, a fact that help it retain archrival Apple as a foundry customer.

Only a handful of papers at ISSCC described designs using TSMC’s 16nm process. Expect many more next year as well as perhaps the first papers of foundry customers using Intel’s 14nm FinFET process.
In the hallways at ISSCC, I sought out topic experts to get their opinions on paper sessions they attended. Behzad Razavi of UCLA said he saw a trend to soft radio with transmitters reduced to DSPs linked to small ADCs and antennas, although receivers still require more complex analog circuits.
You don’t have to go to the cloud for analytics, said Chris van Hook, a medical electronics specialist at the Imec institute outside Brussels. More self-learning algorithms are getting embedded at node-level chips in papers he saw.

Jim Warnock, a designer of IBM mainframe processors, aid he was most fascinated by papers in the low-power digital track. “Some of them are running at a few hertz off picowatts with way different kinds of circuit designs…it’s a different world,” he said.

Indeed, I ran into one post-doc from Berkeley who told me aboutstartup Psikick that is designing integrated IoT chips that aim to run off energy harvesters. He said he hopes to launch his own IoT chip startup eventually.

Back at the high end, analyst David Kanter of the Linley Group said IBM’s mainframe chip designers will be challenged to continue differentiate their processors as they increasingly move to off-the-shelf technologies. If a landmark fab sale goes through as expected, the group will design its next zSeries chips in a 14nm process run by Globalfoundries.

IBM’s Warnock expressed confidence he has a laundry list of accelerator blocks for analytics and mainframe functions he can imagine integrating into future mainframe chips. And he said he hopes to design chips made in Globalfoundries’ giant Malta, New York fab.

The event echoed with groans of designers trying to squeeze more out of increasingly complex and costly process nodes. “We should keep on scaling to 7 and 5nm but we need to harvest the sweet nodes,” said Geoffrey Yeap, vice president of technology at Qualcomm, speaking on an evening panel on Moore’s Law.

Liam Madden rallied for the 2.5-D chip stacks he is helping create at Xilinx, the latest of which will use a 20nm process pack 19 billion transistors including 10 ARM A9 cores. With two new metal layers added in the latest nodes, “the RC delays are killing you routing across chip,” he said.

Paolo Gargini who leads the ITRS semiconductor road map effort said chip stacks are today what high-K metal gate design was in 2007, the next big requirement for progress.

Intel fellow Mark Bohr disagreed. “We need vertical interconnects one or two orders of magnitude more dense than today’s through-silicon vias,” he said
.
Madden agreed but expressed confidence TSV density “will go up at least an order of magnitude in the next two or three years, but getting beyond that will be tricky.”

Despite the pains of progress, engineers showed plenty of silicon innovations at the event. The follow pages cull out a few of them.

Next Page: Tiny sensor, solar core

What I saw at ISSCC 2015:

• Page 1: Intel, Xilinx debate 3-D chip stacks
• Page 2: Tiny sensor, solar core
• Page 3: Enabling modular smartphones
• Page 4: Smartphones squawk in 4K
• Page 5: Lightning fast links
• Page 6: Heads up display and brain monitor
• Page 7: Bluetooth hits new low
• Page 8: The x86 hits lows and highs
• Page 9: Thin and light innovations
• Page 10: Microservers and mega-transceivers