3D NAND and TSV Process

The article below discusses the development of 3D NAND flash memory. The explanation of the difficulty of creating these 3D structures uses the term Through Silicon Via (TSV) to explain how to connect vertically between layers that are one above the other inside an IC chip.

However, TSV is used only when we are connecting between individual silicon IC chips one to another. Holes are drilled through each chip to connect them electrically when they are stacked on top of each other.

See 3DSemiconductors-TSV w/ DRAM Memory.

Samsung and its competitors are building the 3D  NAND transistors inside each chip. This 3D approach has its own difficulties of connecting all the vertical layers one to the next.

See more at 3D NAND Flash Advances and at Samsung 3DStacked NAND Flash has Engineering Samples

Ron

Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Silicon bungalow? Nah, I'll have SK Hynix's 4-storey flash condo

Chip-embiggening 3D NAND wizardry expands upwards

By Chris Mellor, 28 Apr 2014 

DRAM and flash fabber SK Hynix is set to mass produce 3D NAND by the end of this year, while Micron Technology sees its own 3D mass production kicking in during the second half of 2015.

By building NAND chips with layers of current planar cells (known as 2D NAND) the amount of capacity in a chip's footprint can be raised without needing to go to smaller flash cell geometries.

With smaller cell sizes, its working life (endurance) goes down while its error rate goes up. SanDisk has just announced a 15nm process (1Z), moving down from the 19nm (1X) size used by it and its fab partner Toshiba.

Samsung has SSDs available using 19nm technology. SK Hynix began full-scale production of 16nm flash chips at the end of 2013.

Micron expects to have a 16nm SSD in the first half of this year. This can keep it going on the capacity raising front but it seems unlikely that it, and the industry will move to sub-15nm cell sizes because of these scaling-related problems.

That means its ability to increase planar chip capacity without increasing the chip's footprint size will come to an end, and so 3D NAND, with stacked planar layers, is seen as the answer to increasing capacity requirements until some denser 2D post-NAND technology becomes available.

Think of 3D flash cells as being like condos – blocks of apartments in a housing estate – with planar cells being single-storey dwellings. You can house more people in a fixed estate area using 4-storey condos than you can with single storey homes.
Hypothetically, if a 128Gbit planar chip is possible with 16nm NAND while, say, only 64Gbit is available with 19nm NAND, a 4 layer 19nm chip could provide 256Gbits. That's twice the capacity of the planar 16nm chip but within the same footprint. An 8-layer, 19nm 3D chip could provide 512Gbits, trouncing the 16nm planar cell's 128Gbit capacity.

A 4-layer, 16nm cell chip could provide 512Gbit capacity and an 8-layer chip 1,024 Gbits, making for lots of decent selling conversations between NAND chip reps and tablet/mobile phone suppliers.

It's not going to be as simple as this because vertical tunnels between the layers are needed to connect them to a base layer of logic circuitry. These connecting holes, Through-Silicon Vias (TSVs), use up some of each chip layer's area. The more layers you have, the more TSVs you need, thus (we understand) you need more logic in the base layer. Consequently the production and testing process becomes more and more complicated.

SK Hynix began full-scale production of 16nm flash in June, 2012, and moved to a 2nd gen process at the end of 2013. If it can get the number of layers high enough in its coming 3D chips then it could gain a significant capacity advantage over its competitors' planar chips.

The company is also aiming to introduce its own flash controllers and produce 3-layer cell (TLC) NAND using its 16nm technology.

Toshiba, SanDisk 15nm MLC/TLC NAND

Partners Toshiba and SanDisk have developed 15-nanometer process technology for NAND flash memory...will replace the second-generation 19-nm process technology when production begins at Toshiba’s plant in Yokkaichi, Japan, Toshiba said. 

More below.

Ron

Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Toshiba, SanDisk start mass production of 15nm NAND memory

April 23rd, 2014 at 11:05 am - AuthorAnton Shilov

Toshiba Corp. and SanDisk Corp. on Wednesday said that they would start to produce multi-level cell (MLC) NAND flash memory using 15nm fabrication process later in April. The new manufacturing technology allows Toshiba to make world’s smallest and potentially cost-efficient 128Gb NAND flash memory.

Initially, Toshiba and SanDisk will produce 128Gb MLC (two-bits-per-cell) MLC NAND flash memory using the 15nm process technology at Fab 5 phase one, where the fabrication tech will replace the companies’ second-gen 19nm manufacturing process. The phase stage of Fab 5 is currently under construction, and the new technology will also be deployed there.

The new 128Gb MLC NAND flash chips achieve the same write speed as chips formed with second generation 19nm process technology, but boost the data transfer rate to 533Mb/s, 30 per cent faster, by employing a higher speed interface.

Toshiba claims that it had achieved the world’s smallest class chip size with the 15nm process and improved peripheral circuitry technology.

According to SanDisk, the 15nm technology uses numerous progressive process innovations and cell-design solutions to scale the chips along both axes. SanDisk’s All-Bit-Line (ABL) architecture, which contains proprietary programming algorithms and multi-level data storage management schemes, has been implemented in the 1Z technology to deliver NAND flash solutions with no sacrifice in memory performance or reliability. SanDisk’s 1Z technology will be utilized across its broad range of solutions, from removable cards to enterprise SSDs.

Separately, Toshiba announced that it would use the 15nm fabrication process to produce triple-level-cell (TLC, three-bits-per-cell, 3bpc) NAND flash memory. Such memory, provided that the yields are sufficient, will be the world’s most cost-efficient NAND flash. The company aims to start mass production of TLC NAND using 15nm process in June, 2014.

The company intends to develop controllers for 3bpc embedded NAND flash memory in parallel and introduce TLC NAND products for smartphones and tablets. Eventually Toshiba will use 15nm TLC NAND with special controllers for solid-state drives.

Toshiba and SanDisk run joint NAND flash manufacturing operations in Japan.

KitGuru Says: If Toshiba and SanDisk manage to sustain 3000 write/erase cycles with 15nm MLC NAND (typical amount of cycles sustained by modern MLC), then the new memory type will enable lower-cost SSDs already this year. In case the new type of memory (like 15nm TLC NAND) requires new controllers, then its adoption will take time.

Galaxy S5 BOM $256, iPhone $191, $173

IHS released a teardown of Samsung’s Galaxy S5, the estimated bill of materials of $256 BOM keeps going up from previous cell phone generations. See more in the article below;

"IHS found that the Galaxy S3 had a BOM of $205, while the S4 ended up at $233 (LTE version with Qualcomm 600 SoC). On top of that, a Galaxy S series phone costs upwards of $8 to assemble."

While "the iPhone 5S had a BOM of $191 when it launched last September, while the iPhone 5C had $173 worth of components inside its unapologetically plastic body."

Like in Apple's phone DRAM and NAND are a high cost items and as semiconductor manufacturing advance along its learning curve it will increase Samsung margin.

1. 1080p display is the most expensive component, costing about $65
2. DRAM and NAND memory is around $33
3. Unclear how much the Snapdragon 801 SoC costs, should be about $30

See more at iPhone Teardown Updated,  iPhone 5s Teardown, and some more about the processor iPhone A6 Teardown Update

Ron

Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

$256, priciest Galaxy S to date

Research firm IHS got hold of Samsung’s new flagship smartphone and took it apart to the last bolt to figure out how much it actually costs to build. According to the teardown, the Galaxy S5 has a bill of material (BOM) of $256. 

Of course, this is not the full cost of the device, as it does not cover logistics, R&D, marketing and a range of other expenses that Samsung has to cover before the device makes it to retail.

Galaxy S5 BOM higher than usual

The $256 figure sounds a tad too high. Most flagship phones tend to have a BOM of about $200 or less. Most iPhones usually end up south of $200. For example, the iPhone 5S had a BOM of $191 when it launched last September, while the iPhone 5C had $173 worth of components inside its unapologetically plastic body. 

The Galaxy S5 retails for $699. Samsung does not have as much room to jack up margins as Apple does on the iPhone 5S, but it still has quite a bit more than many manufacturers. What’s more, Samsung’s BOM keeps going up. IHS found that the Galaxy S3 had a BOM of $205, while the S4 ended up at $233 (LTE version with Qualcomm 600 SoC). On top of that, a Galaxy S series phone costs upwards of $8 to assemble.

High-end smartphones are pricey, but at least it’s nice to see that Samsung’s consumers get a bit more value for money with each new generation.

Display remains the priciest component

Unsurprisingly Samsung’s 5-inch 1080p display is the most expensive component in the Galaxy S5. IHS puts its cost at $65. The cost of DRAM and NAND memory is around $33, but it’s unclear how much the Snapdragon 801 SoC costs. IHS puts the price of the Snapdragon 600 used in the S4 at $20, while the big Exynos 5 was estimated to cost $30. The Snapdragon 801 is probably closer to the Exynos in terms of overall cost.

“Inside we see mostly a lot of recycled components that we’ve seen before. There’s really nothing special inside where Samsung is pushing the envelope,” IHS analyst Andrew Rassweiler toldRe/code. “There’s no breakthroughs, there’s nothing earth-shattering. It’s really just a continuation of what has come before.”

However, although there are no breakthroughs, the Galaxy S5 features a few new sensors, including a $4 fingerprint sensor and a biosensor from Maxium, with an estimated cost of $1.45. In addition to the new components which were not used in previous Galaxy S phones, the S5 also features a somewhat sturdier body, which also happens to be waterproof. This probably added a few more bucks to the BOM. 

Qualcomm's SoC Road Map for 2014, 2015

The table in the article below documents Qualcomm direction in response to Apple 64 bit processor (see in September 2013 iPhone 5s Teardown ).

"Today Qualcomm is rounding out its 64-bit family with the Snapdragon 808 and 810. Like the previous 64-bit announcements (Snapdragon 410, 610 and 615), the 808 and 810 leverage ARM's own CPU IP in lieu of a Qualcomm designed microarchitecture. We'll finally hear about Qualcomm's own custom 64-bit architecture later this year, but it's clear that all 64-bit Snapdragon SoCs shipping in 2014 (and early 2015) will use ARM CPU IP."

A key issue for Qualcomm is "Qualcomm's sharing the roadmap to its premium Snapdragon chipset lineup much earlier than it usually does; the 810 and 808 won't be available on devices until the first half of 2015. This is largely due to competitive pressure: MediaTek, Intel and NVIDIA are going big by pushing out chips with 64-bit support and, in some cases, eight cores. Given how fast the industry is iterating, it's not hard to see that Qualcomm -- which currently dominates much of the mobile chipset market -- doesn't want to lose momentum or popularity." Qualcomm's 2015 chips may make you regret getting a new phone this year

See more from September 2013 on iPhone 5s Teardown ,

and from July 2013 Smartphone: MediaTek Overtaking Qulacomm

While Qualcomm grew 31% last year, Media Tek already grew 36% semiconductor vendors ranking - Top Semiconductor Ranking for 2013

Ron

Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Qualcomm'sSnapdragon 808/810: 20nm High-End 64-bit SoCs with LTE Category 6/7 Support in2015

by Anand Lal Shimpi on April 7, 2014

Today Qualcomm is rounding out its 64-bit family with the Snapdragon 808 and 810. Like the previous 64-bit announcements (Snapdragon 410, 610 and 615), the 808 and 810 leverage ARM's own CPU IP in lieu of a Qualcomm designed microarchitecture. We'll finally hear about Qualcomm's own custom 64-bit architecture later this year, but it's clear that all 64-bit Snapdragon SoCs shipping in 2014 (and early 2015) will use ARM CPU IP.

While the 410, 610 and 615 all use ARM Cortex A53 cores (simply varying the number of cores and operating frequency), the 808 and 810 move to a big.LITTLE design with a combination of Cortex A53s and Cortex A57s. The latter is an evolution of the Cortex A15, offering anywhere from a 25 - 55% increase in IPC over the A15. The substantial increase in performance comes at around a 20% increase in power consumption at 28nm. Thankfully both the Snapdragon 808 and 810 will be built at 20nm, which should help offset some of the power increase.

Qualcomm's 64-bit Lineup
	Snapdragon 810	Snapdragon 808	Snapdragon 615	Snapdragon 610	Snapdragon 410
Internal Model Number	MSM8994	MSM8992	MSM8936	MSM8939	MSM8916
Manufacturing Process	20nm	20nm	28nm LP	28nm LP	28nm LP
CPU	4 x ARM Cortex A57 + 4 x ARM Cortex A53 (big.LITTLE)	2 x ARM Cortex A57 + 4 x ARM Cortex A53 (big.LITTLE)	8 x ARM Cortex A53	4 x ARM Cortex A53	4 x ARM Cortex A53
ISA	32/64-bit ARMv8-A	32/64-bit ARMv8-A	32/64-bit ARMv8-A	32/64-bit ARMv8-A	32/64-bit ARMv8-A
GPU	Adreno 430	Adreno 418	Adreno 405	Adreno 405	Adreno 306
H.265 Decode	Yes	Yes	Yes	Yes	No
H.265 Encode	Yes	No	No	No	No
Memory Interface	2 x 32-bit LPDDR4-1600	2 x 32-bit LPDDR3-933	2 x 32-bit LPDDR3-800	2 x 32-bit LPDDR3-800	2 x 32-bit LPDDR2/3-533
Integrated Modem	9x35 core, LTE Category 6/7, DC-HSPA+, DS-DA	9x35 core, LTE Category 6/7, DC-HSPA+, DS-DA	9x25 core, LTE Category 4, DC-HSPA+, DS-DA	9x25 core, LTE Category 4, DC-HSPA+, DS-DA	9x25 core, LTE Category 4, DC-HSPA+, DS-DA
Integrated WiFi	-	-	Qualcomm VIVE 802.11ac 1-stream	Qualcomm VIVE 802.11ac 1-stream	Qualcomm VIVE 802.11ac 1-stream
eMMC Interface	5.0	5.0	4.5	4.5	4.5
Camera ISP	14-bit dual-ISP	12-bit dual-ISP	?	?	?
Shipping in Devices	1H 2015	1H 2015	Q4 2014	Q4 2014	Q3 2014

The Snapdragon 808 features four Cortex A53s and two Cortex A57s, while the 810 moves to four of each. In both cases all six/eight cores can be active at once (Global Task Scheduling). The designs are divided into two discrete CPU clusters (one for the A53s and one for the A57s). Within a cluster all of the cores have to operate at the same frequency (a change from previous Snapdragon designs), but each cluster can operate at a different frequency (which makes sense given the different frequency targets for these two core types). Qualcomm isn't talking about cache sizes at this point, but I'm guessing we won't see anything as cool/exotic as a large shared cache between the two clusters. Although these are vanilla ARM designs, Qualcomm will be using its own optimized cells and libraries, which may translate into better power/performance compared to a truly off-the-shelf design.

The CPU is only one piece of the puzzle as the rest of the parts of these SoCs get upgraded as well. The Snapdragon 808 will use an Adreno 418 GPU, while the 810 gets an Adreno 430. I have no idea what either of those actually means in terms of architecture unfortunately (Qualcomm remains the sole tier 1 SoC vendor to refuse to publicly disclose meaningful architectural details about its GPUs). In terms of graphics performance, the Adreno 418 is apparently 20% faster than the Adreno 330, and the Adreno 430 is 30% faster than the Adreno 420 (100% faster in GPGPU performance). Note that the Adreno 420 itself is something like 40% faster than Adreno 330, which would make Adreno 430 over 80% faster than the Adreno 330 we have in Snapdragon 800/801 today.

Also on the video side: both SoCs boast dedicated HEVC/H.265 decode hardware. Only the Snapdragon 810 has a hardware HEVC encoder however. The 810 can support up to two 4Kx2K displays (1 x 60Hz + 1 x 30Hz), while the 808 supports a maximum primary display resolution of 2560 x 1600.

The 808/810 also feature upgraded ISPs, although once again details are limited. The 810 gets an upgraded 14-bit dual-ISP design, while the 808 (and below?) still use a 12-bit ISP. Qualcomm claims up to 1.2GPixels/s of throughput, putting ISP clock at 600MHz and offering a 20% increase in ISP throughput compared to the Snapdragon 805.

The Snapdragon 808 features a 64-bit wide LPDDR3-933 interface (1866MHz data rate, 15GB/s memory bandwidth). The 810 on the other hand features a 64-bit wide LPDDR4-1600 interface (3200MHz data rate, 25.6GB/s memory bandwidth). The difference in memory interface prevents the 808 and 810 from being pin-compatible. Despite the similarities otherwise, the 808 and 810 are two distinct pieces of silicon - the 808 isn't a harvested 810.

Both SoCs have a MDM9x35 derived LTE Category 6/7 modem. The SoCs feature essentially the same modem core as a 9x35 discrete modem, but with one exception: Qualcomm enabled support for 3 carrier aggregation LTE (up from 2). The discrete 9x35 modem implementation can aggregate up to two 20MHz LTE carriers in order to reach Cat 6 LTE's 300Mbps peak download rate. The 808/810, on the other hand, can combine up to three 20MHz LTE carriers (although you'll likely see 3x CA used with narrower channels, e.g. 20MHz + 5MHz + 5MHz or 20MHz + 10MHz + 10MHz).

Enabling 3x LTE CA requires two RF transceiver front ends: Qualcomm's WTR3925 and WTR3905. The WTR3925 is a single chip, 2x CA RF transceiver and you need the WTR3905 to add support for combining another carrier. Category 7 LTE is also supported by the hardware (100Mbps uplink), however due to operator readiness Qualcomm will be promoting the design primarily as category 6.

There's no integrated WiFi in either SoC. Qualcomm expects anyone implementing one of these designs to want to opt for a 2-stream, discrete solution such as the QCA6174.

Qualcomm refers to both designs as "multi-billion transistor" chips. I really hope we'll get to the point of actual disclosure of things like die sizes and transistor counts sooner rather than later (the die shot above is inaccurate).

The Snapdragon 808 is going to arrive as a successor to the 800/801, while the 810 sits above it in the stack (with a cost structure similar to the 805). We'll see some "advanced packaging" used in these designs. Both will be available in a PoP configuration, supporting up to 4GB of RAM in a stack. Based on everything above, it's safe to say that these designs are going to be a substantial upgrade over what Qualcomm offers today.

Unlike the rest of the 64-bit Snapdragon family, the 808 and 810 likely won't show up in devices until the first half of 2015 (410 devices will arrive in Q3 2014, while 610/615 will hit in Q4). The 810 will come first (and show up roughly two quarters after the Snapdragon 805, which will show up two quarters after the recently released 801). The 808 will follow shortly thereafter. This likely means we won't see Qualcomm's own 64-bit CPU microarchitecture show up in products until the second half of next year.

With the Snapdragon 808 and 810, Qualcomm rounds out almost all of its 64-bit lineup. The sole exception is the 200 series, but my guess is the pressure to move to 64-bit isn't quite as high down there.

What's interesting to me is just how quickly Qualcomm has shifted from not having any 64-bit silicon on its roadmap to a nearly complete product stack. Qualcomm appeared to stumble a bit after Apple's unexpected 64-bit Cyclone announcement last fall. Leaked roadmaps pointed to a 32-bit only future in 2014 prior to the introduction of Apple's A7. By the end of 2013 however, Qualcomm had quickly added its first 64-bit ARMv8 based SoC to the roadmap (Snapdragon 410). Now here we are, just over six months since the release of iPhone 5s and Qualcomm's 64-bit product stack seems complete. It'll still be roughly a year before all of these products are shipping, but if this was indeed an unexpected detour I really think the big story is just how quickly Qualcomm can move.

I don't know of any other silicon player that can move and ship this quickly. Whatever efficiencies and discipline Qualcomm has internally, I feel like that's the bigger threat to competing SoC vendors, not the modem IP.