Tuesday, November 13, 2012

FinFET Layout Design Rules and Variability

It is not simple to design circuits with FinFET transistors. Layout, 3D dimensions, and shape considerations are described in the article below. Some additional information about Intel's 22nm 3D Tri-Gate FinFETs Transistors.


FinFET structure design and variability analysis enabled by TCAD

Victor Moroz, Synopsys Inc.

10/8/2012 10:14 AM EDT

The introduction by Intel of FinFET transistors at the 22nm mode culminates many years of research and development of a replacement transistor to the immensely successful planar MOSFET whose progressive miniaturization is largely responsible for the electronics revolution. The need for a successor to the planar MOSFET had long ago been identified. Starting with the 90nm process node, improved transistor performance was achieved with the introduction of stress into the transistor channel in a way that boosts the speed of the electrons and holes traveling within it. However, controlling the transistor leakage in the off-state became progressively more difficult. Keeping the electrons and holes under the electrostatic control of the gate electrode is key to controlling leakage current, but a number of so-called short channel effects undermine the gate control. The introduction of high-k dielectrics as the gate insulator at the 45nm process node effectively extended the life of the planar MOSFET for another two process nodes, but by the 22nm process node the planar MOSFET could hardly offer an attractive balance of performance and leakage.

Intel’s FinFETs thus mark the first fundamental change in transistor architecture since the time when the MOSFET replaced the bipolar transistor as the transistor of choice for logic applications. Its performance improvements over the preceding process node (see table) are a clear indication of the promise this technology holds. Although the manufacturing of FinFETs is more complex than manufacturing of its planar predecessor, Intel’s introduction is a testament to the inevitability of these devices....   More at FinFET Layout Design and Variability

No comments:

Post a Comment