Thursday, November 1, 2012
Intel's 14nm Process and Manufacturing Roadmap
foundaries venturing into the FinFET devices it is interesting to see Intel's direction.
The article below with Mark Bohr, senior fellow at Intel, review the road map pertaining to a wide range of manufacturing and design issues. Some of the key points in the article are:
* Intel is sticking with bulk CMOS instead of SOI.
* FinFET transitors are scalable to 14nm process.
* "3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you’re trying to serve. For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution"
Additional information about Intel's 22nm at Tutorial: Intel 22nm 3D Tri-Gate FinFETs Transistors and at Intel’s 22-nm Tri-gate Transistors Exposed
Deep Inside Intel
By Ed Sperling
Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends.
SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel?
Bohr: For a process module as critical as lithography, Intel always has more than one option we pursue. In this era, the options are either EUV or 193nm immersion with multi-patterning.
SMD: How about directed self-assembly?
Bohr: That’s not a universally usable approach. You still need to define some layers with direct patterning, not a self-assembly technique. That’s a niche direction that will not replace these mainstream lithography techniques, but there may be some layers where it can complement the normal patterning techniques.
SMD: What’s your opinion about the future of the foundry business?
Bohr: The traditional foundry model is running into problems. In order to survive, the foundries will have to become more like an integrated device manufacturer. Even some of the chief spokespeople for the foundries have said something similar. The foundry model worked well when traditional scaling was being followed and everybody knew where we were headed. In this era, where you continually have to invent new materials and new structures, it’s a lot tougher being a separate foundry and maskless design house. Being an IDM, we have design and process development under one roof. That’s really a significant advantage.
SMD: Can even Intel afford to be an independent IDM? The cost of building state-of-the-art fabs at future nodes is astronomical.
Bohr: Yes. We have the volume and the products that can fill multiple fabs.
SMD: But you’ve also opened up your fabs to at least a couple customers. Are you planning on extending that? ,
Bohr: Our motivation is that we know we have great process technology, and partnering with other strategic companies can be a win-win situation. We can sell our technology and make more money off what we’ve developed, and they can have some very compelling products. It’s not Intel’s goal to be a general-purpose foundry, but we will be partnering where it makes strategic sense.
SMD: Is Intel sticking to bulk CMOS or will move to new materials such as fully depleted SOI?
Bohr: We see more advantages in bulk than SOI. I won’t say SOI won’t be in the future. There may be some device structure that is better done in SOI than bulk. But I don’t see than happening right now. When we first announced that we were making TriGate or finFET devices at 22nm, we said we’re making these devices on SOI, as well. But we think there are cost advantages to doing TriGate on bulk rather than SOI. That’s our plan for the foreseeable future.
SMD: What comes after the current finFET?
Bohr: The finFET is scalable to 14nm.
SMD: But if you’re at 22nm, 14nm isn’t very far away, so you’ve got to be working on the next step.
Bohr: For Intel, you’re right. For other companies, it’s many years away. For 10nm, which is where I’m spending most of my time these days, I know we have a solution. I can’t elaborate at this point.
SMD: At 10nm aren’t you running into quantum effects?
Bohr: Everything gets different and tougher, but the problems are solvable—at least at that generation.
SMD: How far ahead can you see?
Bohr: I know we can get to 10nm. Beyond that, our research group is working on solutions for 7nm and 5nm. I have confidence we’ll have solutions for those. But by the time we’re down to 5nm we’ll be looking at non-familiar devices and device structures. That’s what we’ll have to do to get down to that level.
SMD: Where do stacked die fit into your roadmap?
Bohr: 3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you’re trying to serve. For a small handheld application where a small footprint and form factor are key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution.
SMD: Along those lines, does Intel see the smart phone and small mobile device market as a key direction?
Bohr: Intel is very serious about getting into the smart phone and tablet markets. We are a very different company from what we were five or six years ago. We are developing process technologies, but also products, that span a much wider range of performance and power than anywhere in our history. We’re not just after the high-performance desktop. We’re developing products that support 100-watt server chips down to sub-1 watt smart phone chips.
SMD: There are a number of interesting techniques Intel is working with, such as near-threshold computing. How will power management start changing inside these chips?
Bohr: When you’re talking about developing a smart phone chip that is ultra low power that also provides improved performance features that the market expects, you have to pull every trick out of the bag. You need great transistor technology, great package technology, great CPU architectures, the ability to turn off parts of the chip when you don’t need them so you’re saving power, the software links with the chip design so the software knows when to throttle power down. You need transistors, CPU architecture and software to be effective in that space.
SMD: How many cores will be required in the future?
Bohr: It depends on the market. In the server market, the more cores you can pack on the better. But in desktops, laptops and smart phones, there’s probably a limit to how many cores are practical. It’s not one. It’s probably several.
SMD: But less than eight?
Bohr: Yes, probably less than eight. But when you talk about the number of cores and computing engines, it depends on whether you’re dealing with traditional computing tasks where four cores are better than two cores. If you’re talking about execution engines in a graphics processor, clearly you want more cores.
SMD: What does this do for Intel’s platform strategy, particularly as you go after many markets with very specific needs?
Bohr: Even for Intel there are probably an optimal number of chip designs. It’s not like in the past where we tried to make one size fit all or have one chip serve multiple markets. But on the other hand, trying to design and manufacture dozens of very different designs in a generation is also impractical. There’s an optimal number of designs, although I don’t know what that number is, that can best meet the market requirements. You want to make as few iterations between the different designs as you can or re-use the cores or some of the circuit blocks between the different chips so you’re not completely redesigning it.
SMD: Are there other materials being considered for transistors?
Bohr: Our research group has been publishing papers about using 3-5 materials http://en.wikipedia.org/wiki/List_of_semiconductor_materials for the channels. You deposit indium phosphide or gallium arsenide layer on top of silicon to make a transistor on the surface. It’s still a silicon wafer, but you’re looking at depositing more exotic materials. That’s new and different and it may happen, but it’s not yet fully resolved how good that approach may be.
SMD: Has the priority for what you’re designing into a chip changed? Is it still all about performance, or has power overtaken that?
Bohr: Ten or 15 years ago, performance was the main goal in developing a new process technology. That really has gone away as the No. 1 priority. We still strive to provide a performance boost with each new technology, but there’s much more emphasis on improving power or efficiency on each new generation. We do that by reducing active power for the work a chip does. That’s a much more important goal for us today. Part of the reason is that the market has shifted from desktop applications to more mobile products. The first transition was from desktops to laptops. Now the move is to put things into smart phones. Today’s consumer wants computing power he can hold in his hand in the form factor of a smart phone and a tiny battery. He wants the performance he had on his laptop only three or four years ago. That’s what we shoot for.
SMD: That shifts the biggest challenge to the architecture, right?
Bohr: Yes. Whether it’s low-power, low-leakage transistors or a more efficient core architecture—or linking that with more efficient software.
SMD: What becomes the next big bottleneck?
Bohr: We have lots of challenges. Lithography is the key challenge in making transistors smaller. Whether EUV will happen on time or we have to extend immersion using multiple patterning. But when you make transistors smaller they don’t become less leaky. In fact, the opposite is true. You have to continually invent new structures and materials to allow feature-size scaling, which is critical for active power reduction and for cost.
SMD: But wires don’t scale well. How do you deal with that?
Bohr: RC delay gets worse as you scale, compared with transistors, which tend to get faster as you scale down. The industry has had 20-plus years of struggling with that problem. One way we’ve addressed that is that we’re no longer striving for very high operating frequency, especially in the phone market where 2 or 2.5GHz would probably be sufficient. That’s one advantage. The other advantage is that the average size of the chips is smaller in these laptop and cell phone applications so you don’t have interconnects traveling a long distance across a large chip. Instead, it’s a more compact chip so the signals don’t have to go as far. But even with those chips, we still have a challenge of performance from the interconnect. We have to be clever about what pitches we choose. Some of the lower layers are dense pitch, where density is important. Some of the upper layers are coarser pitch, where performance is important. We’re also continuing to drive down interconnect capacitance by employing lower-k dielectrics.
SMD: Is the interconnect becoming more problematic?
Bohr: If you talk to a designer 10 years ago you would have heard the same thing. Maybe now they’re saying, ‘This time we’re really serious.’
SMD: How about new interconnect technology?
Bohr: It’s hard to replace copper and low-k other than by making lower k. But at least in the low-power cell phone market, stacking chips does help to minimize some of the interconnect issues, particularly between the logic and the memory chips.
SMD: You’re referring to through-silicon vias?
SMD: So if Intel is planning to get into that market, the company is experimenting with that technology right now?
Bohr: Yes, and we’ve been public about exploring TSV and 3D technology for a couple years. Although there are some challenging technology aspects, the real issue is cost. Doing TSVs and stacking chips—especially these custom Wide I/O chips—is expensive. So this might be a better engineering solution in terms of density, performance and power, but will the market bear the added cost? Not all markets will bear the higher cost.