3D Flash NAND Devices and Process

The article below discusses developments in 3D Flash NAND. Toshiba and Macronix have different approaches. See more details about Toshiba Next NAND- 3D with 15 Layers.


Applied material discusses processing issues and new equipment to address them.

"According to Applied Materials, building 3D NAND structures in like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata."

Ron Maltiel
www.maltiel-consulting.com





3D NAND flash is coming

http://www.edn.com/electronics-blogs/practical-chip-design/4401542/3D-NAND-flash-is-coming

Brian Bailey - November 15, 2012

Flash memory has very quickly risen from being an obscure memory type to perhaps becoming the dominant memory type for many devices, including music players, cell phones, tablets and now increasingly servers and mainstream PCs. But flash memory does not scale quite as well as the more traditional DRAM that it is replacing. It is thought that DRAM can scale down to 1nm whereas we are already hitting some problems with the scaling of the floating gate in NAND flash. It is not thought that planar NAND can go below 10nm which is only a couple of processes steps away from where we are today.


There are several other types of memory being developed, including spin-torque MRAM and Resistive RAM (ReRAM) that may replace both RAM and flash in the future. Another exciting direction is 3D NAND structures. In some respects this is similar to FinFET development for traditional transistors that are finding their way into 20nm and 14nm processes.


Toshiba is one company pushing 3D NAND processes with its p-BiCS (pipe-shaped Bit Cost Scalable) technology. The thought is that rather than lay the cells flat on the surface, higher densities can be achieved by stacking them on top of each other. This is shown diagrammatically in the figure below. As you can see this is not the same as 3D ICs where multiple substrates are layered on top of each other and connected using through silicon vias (TSV), this is building cells on top of each other to create U shaped bit lines. They currently have 16 layers devices where the hole size is 50nm and Toshiba says that the process becomes cheaper than the traditional NAND processes when more than 15 layers are created. Samples are expected next year and volume shipments by 2015...
  Additional details

Toshiba Next NAND- 3D with 15 Layers

The winner for the next flash memory approach is still not clear. A strong candidate is stacking memory NAND dies one on top of another. The dies are connected using Through Silicon Vias (TSV). Toshiba has a different approach to 3D " not stacking NAND chips one atop the other but rather stacking layers of NAND in a single chip" See more details below.

The key concern for next NAND generations is the 5 years lead time to build a new $5 billion fab, which could be designed for the wrong process technology.

It does not help that "the number of electrons in a gate decreases as the process geometry size is reduced....below 10nm the number of critical electrons in a gate can be as few as 10 – and that losing 10 electrons could seriously affect the gate's functioning. He says there are a variety of issues with such very small cells, such as bit-line loading, interference and leakage, leading to signal retention and reliability issues, for which, currently, there are no solutions.

These problems may make 10nm NAND technology impractical and sub-10nm impossible. Park suggests that 3D stacking, putting dies on on top of another, could be away out of this trap. He charts various approaches and identifies issues with each one, mentioning yield and retention as overall issues" (see more at Flashboys: HEELLLP, we're trapped in a process size shrink crunch)

Ron
www.maltiel-consulting.com



The 3D die stack tack: Toshiba builds towering column of flash


Resistance is futile
By Chris Mellor, 15th October 2012 09:28 GMT


Toshiba is building high rise flash and ReRAM chips, with prototypes coming next year and volume shipping in 2015.

The idea of high-rise or 3D chips is that we can sidestep limitations on increasing the storage density of flash or memory chips by stacking them one on top of the other, increasing the storage density on a Mbits/in 2 basis by building upwards, in the same way as high-rise housing increases the number of people living in the ground footprint of a block of flats.

Hot on the heels of our story about the NAND scaling trap [1], with 3D NAND and ReRAM suggested as two of the potential escape routes, we learn from Nikkei Electronics [2] that Toshiba is building 3D dies using a type of NAND, its p-BiCS (pipe-shaped Bit Cost Scalable) [3] technology, and also a coming replacement technology for NAND, ReRAM (Resistive RAM) which combines attributes of RAM and NAND to provide byte addressability, DRAM-class speed and NAND non-volatility.

As the slide below shows, 3D flash involves layers of NAND dies with communicating holes - TSVs or Through Silicon Vias - linking them to a stack controller at the base of the stack. It is not stacking NAND chips one atop the other but rather stacking layers of NAND in a single chip.

Toshiba p-BiCS technology [4]

Toshiba's p-BiCS NAND has a 50nm-size hole and 16 layers. Toshiba's chief engineer, Masaki Momodomi, at its Semiconductor & Storage Products Co., says that p-BiCS becomes cheaper than ordinary NAND when more than 15 layers are used, presumably comparing similar capacity levels. The company aims to deliver 128Gbit and 256Gbit prototype samples next year, engineering samples in 2014, with volume shipments in 2015; we are more than two years away from seeing product hit the streets.

The ReRAM [5] technology has a similar timescale though at lower capacities. It has much faster write times than NAND and Toshiba sees it fulfilling a different role from p-BiCS, being used closer to CPUs than p-BiCS, with STT-RAM being used for cache memories in, for example, SSDs. This is a similar hierarchy to the one proposed by Hynix in our NAND Scaling Trap story today. Jim Handy of Objective Analysis said; "It makes sense that ReRAM … would be used in performance applications, though. They are far faster at writes than NAND is, they are random access devices which NAND is not, and they don't need ECC. All this lends itself to faster performance."

Toshiba's ReRAM technology will appear in the same sequence of prototype samples, engineering samples and volume production as p-BiCS with the same general timing. A picture of a 64Gbit ReRAM device was shown at the Toshiba briefing attended by Nikkei Electronic but Toshiba intends to deliver generally equivalent p-BiCS and ReRAM capacities.

It is set of reducing the size of its current 1Xnm (19nm) NAND cells, and will target 1Ynm (18-14nm we understand) products this year and 1Znm (10-13nm) products next year.

Handy said: "All those new technologies (MRAM, ReRAM, FRAM...) perform better than NAND (BiCS is a kind of NAND) but are more costly. In memory cost is everything so these alternatives don't do well. The promise of these technologies is that they will move right past NAND's scaling limit. If they do that they will eventually become cheaper than NAND, but not until NAND has stopped scaling for 2 process generations.

"Toshiba talks about 1y and 1z, their processes after 19nm. I suspect that NAND will stop scaling at around 10nm, but BiCS will cause NAND pricing to continue to decline after that. Of course, those geniuses who have been coaxing NAND as far as 19nm could very well keep pulling rabbits out of their hats and push it well beyond 10nm - time will tell."

Will we see continued NAND process size decreases or 3D as the chosen way to get more capacity from a NAND die's footprint? Handy said: "The most recent ITRS [International Technology Roadmap for Semiconductors] [6] roadmap plots out two different directions for NAND - vertical (BiCS) and conventional. The industry really doesn't know where it's going to go, but it has plans in place for either eventuality."

Hynix Developing PCM, MRAM, and ReRAM Flash

To cut down cost and development risk Hynix is working with IBM on PCM type of flash memory. Hynix is already working on other future approaches such as PCM, MRAM, and ReRAM Flash (see more below).

Some background information on PCM, MRAM, and ReRAM Flash at Pushing the PRAM: when chips just can't get any smaller more information is at Flash educational links



Ron





SK Hynix, IBM form chip development alliance
http://www.zdnetasia.com/sk-hynix-ibm-form-chip-development-alliance-62305070.htm
By Ellyne Phneah , ZDNet Asia on June 11, 2012 (9 hours ago)

Summary

Korean chipmaker and Big Blue to develop phase-change random access memory (PcRAM), a non-volatile chip that can store high data volumes, amid rising popularity of mobile devices.



SK Hynix has formed an alliance with IBM to develop phase-change random access memory (PcRAM), which is considered to be the next generation of memory chips and capable of storing high data volumes.

According to Song Hyeon-jeong, head of the SK Hynix's future strategy office in the Korea Times on Sunday, the collaboration will help the Korean chip manufacturer strengthen its capabilities to better compete with rivals in next-generation chips. PcRAM is a non-volatile memory chip which uses the property of chalcogenide glass to switch between both states, and is touted to be able to store a lot of data but is slower than convential dynamic random access-memory (DRAM) chip.

The alliance also reflects efforts to develop advanced chips in light of the rising popularity of smartphones and tablets. SK Hynix said it was unable to survive with existing chips--NAND flash and DRAM--which were expected to be obsolete in a few years, the report noted.


As the chip-making structure of PcRAM was simple, the company said it would save on manufacturing as PcRAM applications would need the corresponding phase-change process to be induced by an electricial current and a significant-higher packing density of information.


SK Hynix since last year also had been working with Japanese chipmaker, Toshiba, on the development of magnetoresistive random access memory (MRAM), which is able to pack memory in a denser manner, according to a seperate report by the Korea Times. The Korean chipmaker had been developing resistive random access memory (ReRAM) with Hewlett-Packard (HP) since 2010, which was found to store twice as much data and use less energy than flash memory.