Monday, December 3, 2012

3D Flash NAND Devices and Process

The article below discusses developments in 3D Flash NAND. Toshiba and Macronix have different approaches. See more details about Toshiba Next NAND- 3D with 15 Layers.

Applied material discusses processing issues and new equipment to address them.

"According to Applied Materials, building 3D NAND structures in like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata."

Ron Maltiel

3D NAND flash is coming

Brian Bailey - November 15, 2012

Flash memory has very quickly risen from being an obscure memory type to perhaps becoming the dominant memory type for many devices, including music players, cell phones, tablets and now increasingly servers and mainstream PCs. But flash memory does not scale quite as well as the more traditional DRAM that it is replacing. It is thought that DRAM can scale down to 1nm whereas we are already hitting some problems with the scaling of the floating gate in NAND flash. It is not thought that planar NAND can go below 10nm which is only a couple of processes steps away from where we are today.

There are several other types of memory being developed, including spin-torque MRAM and Resistive RAM (ReRAM) that may replace both RAM and flash in the future. Another exciting direction is 3D NAND structures. In some respects this is similar to FinFET development for traditional transistors that are finding their way into 20nm and 14nm processes.

Toshiba is one company pushing 3D NAND processes with its p-BiCS (pipe-shaped Bit Cost Scalable) technology. The thought is that rather than lay the cells flat on the surface, higher densities can be achieved by stacking them on top of each other. This is shown diagrammatically in the figure below. As you can see this is not the same as 3D ICs where multiple substrates are layered on top of each other and connected using through silicon vias (TSV), this is building cells on top of each other to create U shaped bit lines. They currently have 16 layers devices where the hole size is 50nm and Toshiba says that the process becomes cheaper than the traditional NAND processes when more than 15 layers are created. Samples are expected next year and volume shipments by 2015...
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