Hynix Next Gen. NAND Flash

In December 2011, at the IEDM conference Hynix presented their version of the next generation of NAND flash (smaller than 20nm). Key developments presented: "A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time.

1) Quad spacer patterning technology (QSPT) of ArF immersion lithography is used for patterning mid-1x-nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as

2) advanced WL air-gap process,

3) floating gate slimming process, and

4) optimized junction formation scheme. And also, by using

5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved."
See more details below.
Ron


A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies
 Joowon Hwang, Jihyun Seo, et al., Hynix Semiconductor Inc.
5/14/2012 3:21 PM EDT
 Editor’s note: This work was first presented at the 2011 IEEE International Electron Devices Meeting (IEDM) and appears here courtesy of the IEEE.

For more information about IEDM 2012 (San Francisco, CA; December 10-12), click here. A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time.
1) Quad spacer patterning technology (QSPT) of ArF immersion lithography is used for patterning mid-1x-nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x-nm design rule NAND flash memories has been successfully realized.

The NAND flash memory cell has been scaled down to the 2x [1,2,3] and 2y nm [4] generations aggressively. As scaling down of a cell size, many serious scaling problems were caused in 2x and 2y nm generation, however they were solved or managed by process, device, and system solutions. For further scaling down beyond 2y nm, we face new scaling limitations such as patterning limitation of ArF immersion spacer patterning technology (SPT), more severe control gate (CG) poly-Si filling problems between floating gates (FGs), and high electric field and charge loss problem between WLs. This paper describes several new advanced processes and operation schemes to overcome these problems, as shown in Table 1. As a result, M1XNAND flash cell is successfully implemented with highly manufacturable integration technologies.

Table 1: Major issues and solution of mid-1x cell technology. M1X-NAND cell process Figure 1 shows the layout of M1X-NAND flash cells. The half pitch of WL is middle-1x nm. The BL contacts are formed staggered arrangement and a string has several dummy WLs. In order to pattern middle-1x nm design rule WLs, QSPT is intensively developed to overcome limitation of ArF immersion SPT. Figure 1: Layout of Mid-1x-nm NAND (M1X-NAND) string with dummy WLs. The half pitch of WL is mid-1x-nm. As shown in Figure 2, first patterns are formed by photolithography and the two times combination of previous formed pattern and spacer are formed final patterns. Figure 2: Schematic diagram of QSPT (Quad Spacer Patterning Technology) key fabrication steps. Two times spacer patterning is used to make mid-1x patterning. The WL critical dimension (CD) of QSPT, which plays a very important role of Vth distribution factor, is precisely controlled less than 1.5% uniformity (see figure 3). QSPT is successfully adopted for mid-1x-nm design rule NAND cell patterning. Figure 3: Location dependence of WL CD variation of QSPT gate patterned NAND string. WL CD is precisely controlled under 1.5% uniformity. Figure 4 shows cross-sectional TEM micrographs of M1X-NAND cell, (a) along WL-direction, and (b) along BL-direction. Figure 4: Cross-section TEM view of the cell, (a) along WL direction, (b) along BL direction. The CGs are well patterned with middle-1x nm half pitch. The floating gate slimming process can achieve the void-free filling of CG poly-Si and wider active area CD, which can obtain large cell current. An electrical depletion in CG poly-Si is greatly suppressed by this void-free process. As a result, BL interference is successfully improved 20% compared with conventional process (see figure 5). The CG CoSi height was selected reasonably to achieve optimized gate shape and decrease WL RC delay for improvement program performance. Figure 5: The simulated results of BL interference with FG slimming scheme. BL interference can be improved to 20%. Cell performance To suppress charge loss (Q-loss) between CG and neighbor FG due to lateral high electric field during program, we have adopted an advanced CoSi-based WL air-gap process that has an air-gap portion above 50% between WLs. As shown in Figure 6(a), the electric field between CG and neighbor FG can be reduced 20% by an advanced CoSi-base WL air-gap. However, reduction electric field by WL airgap is not sufficient to prevent charge loss perfectly because of scale-down issues at mid-1x-nm cell size. So N±1 WL bias control scheme were adopted within WL air-gap. As a result we can also reduce the electric field 15% additionally (see figure 6(a)). Figure 6: (a) Electric field between CG and neighbor FG during programming. (b) 3-D e-field simulation with programmed PV3 neighbor cell. The electric field at point A can be reduced by air-gap and N±1 WL bias control. Then the advanced air-gap and N±1 WL scheme can greatly alleviate charge loss between CG and neighbor FG by decreasing electric field, as shown in Figure 7. Furthermore, as shown Figure 8, PGM speed is improved by N±1 WL scheme, because FG potential of program cell increase by cross coupling effect between WL and neighbor FG. Figure 9 shows the cell coupling ratio with and without air-gap. Cell coupling ratio can be also improved by air-gap due to reducing capacitance of WL direction. Figure 7: Improvement of charge loss with N±1 WL bias control method. Charge loss is greatly decreased to ~300mV by applying Vpass+2V to neighbor N±1 WL. Figure 8: Improvement of PGM speed with N±1 bias control method. Figure 9: Cell coupling ratio as technology shrinkage. Read current reduction is also major issue because of higher bulk doping for suppressing short channel effects in mid-1x-nm cell transistors. A new advanced junction scheme of cell and select transistor is adopted to maximize read current and reduce leakage current in unselected block (see figure 10). Figure 10: Read current with/without select Tr. junction optimization. Read current can be improved by select Tr. junction optimization. Cell Vth Distribution Figure 11 shows cell Vth distributions for the multi-level M1X-NAND cells. The Vth distributions have normal shapes and are well separated to three MLC states. This result confirms that M1X-NAND cell technology can be applied for high density MLC. Figure 11: Three-level programmed Vth distributions of M1X-NAND cells. Vth distributions are well separated to three MLC states. A highly manufacturable mid-1x-nm NAND flash memory (M1X-NAND) has been developed with new integration technologies, such as QSPT, advanced WL air gap process, floating gate slimming process, and optimized junction formation scheme, to overcome scaling limits of mid-1x-nm technology. The excellent device characteristics and reliability are achieved successfully. And also, a new N±1 WL Vpass scheme during programming has been also adopted to overcome WL-to-WL high field issue. Then, we have demonstrated a middle-1x nm-generation NAND flash memory (M1X-NAND) with high performance and reliability. References 1 K. Prall, et al., “25nm 64Gb MLC Technology and Scaling Challenge,” IEEE IEDM Technical Digest, pp. 102-103, 2010. 2. C. Lee, et al., “A Highly Manufacturable Integration Technology for 27nm a and 3bit/cell NAND Flash Memory,” IEEE IEDM Technical Digest, pp. 98-101, 2010. 3. H. Shim, et al., “Highly Reliable 26nm 64Gb MLC E2NAND (Embedded -ECC & Enhanced-efficiency Flash Memory with MSP (Memory Signal Processing) Controller,” VLSI Symp. Technical Digest, pp. 216-217, 2011. 4. K. Lee, et al., “A Highly Manufacturable Integration Technology of 20nm Generation 64Gb Multi-Level NAND Flash Memory,” VLSI Symp. Technical Digest, pp. 70-71, 2011. About the authors This article was contributed by the Flash Device Development & Advanced Process Team, R&D Division, Hynix Semiconductor Inc. The authors include J. Hwang, J. Seo, Y. Lee, S. Park, J. Leem, J. Kim, T. Hong, S. Jeong, K. Lee, H. Heo, H. Lee, P. Jang, K. Park, Myungshik Lee, S. Baik, J. Kim, H. Kkang*, M. Jang*, J. Lee*, G. Cho, J. Lee, B. Lee*, H. Jang, S. Park, J. Kim*, S. Lee, S. Aritome, S. Hong and S. Park

Smartphone Components Cost; NAND Flash, Display, DRAM

Smart phone components
Source: Gartner 

It is interesting that semiconductor memory chips are the largest portion of smart phone cost (see below).

This is another proof of the growth of the flash market vs. DRAM memory.  Dram memory is only $8-10 while Flash is $20-22. (See more at Simon Sze - Inventor of Floating Gate Non Volatile Memory   and in March 16,2012 blog  When will Flash Memory Market be 2x of DRAMs )

Ron






What’s Costliest Part of Smartphone? Hint: It’s Not the Display
By Olga Kharif View ProfileEmailTwitter

http://go.bloomberg.com/tech-blog/2012-05-09-whats-costliest-part-of-smartphone-hint-its-not-the-display/

May 9, 2012 8:08 PM EDT
Posted in Android, Apple, Mobile, Posts
0 Comments inShare.14PrintEmailNomura Equity Research recently released its “2012 Smartphone Guide,” which offers a graphical look at the components that go into phones and their providers’ market shares. More than 25 parts are needed to make a modern smartphone.

What were the interesting takeaways?
The display has been seen as the costliest part of the phone. Not so today, according to Nomura. NAND flash memory costs between $20 and $22 per device on average, as compared with $18 to $20 for the display. That’s good news for memory suppliers Samsung Electronics, Toshiba, SanDisk and Micron Technology. The NAND’s heftier price tag comes as phonemakers like Apple and Samsung increase the amount of memory in their devices.

While Qualcomm is the mobile chip market leader with a 24 percent share, followed by Texas Instruments Inc. with 12 percent, third place is shared by two vendors: STMicroelectronics NV and Taiwanese company MediaTek Inc. — the low-cost supplier that’s been gaining steam. At 9 percent, MediaTek’s share of the mobile semiconductor market last year was higher than that of Intel, Broadcom or Samsung.

Nomura’s graphical guide is big, so we broke it into different chunks below. You can also view the complete chart.

Simon Sze - Inventor of Floating Gate Non Volatile Memory

Floating Gate Non Volatile Memory is a basic building block of Flash memory (see below).


Simon Sze, inventor of floating-gate NVM  Memory
Photo: Josephine Lien, Digitimes, March 2012

It is impressive how far non volatile memory advanced since the early 1980's.  It took it a long time for non-volatile memory to gain market acceptance.

I worked on the first commercial EEPROM (a flavor of NVM) at Intel in 1981.  It was hard to explain to customers what the advantages of EEPROM were.  Sales were small.

The next big advance for the non volatile memory industry was Flash NAND.

I was at the IEDM meeting in 1984 where Toshiba introduced the concept of flash NAND IC.  It took more than ten years for the flash to mature and its market to grow. The first big markets were in digital camera and flash drives.

Now it looks that NAND is going to overtake DRAM volume (When will Flash Memory Market be 2x of DRAMs ).

Ron



Simon Sze and his invention of floating-gate NVM


http://www.digitimes.com/news/a20120418PD211.html?mod=0
Josephine Lien, Taipei; Jessie Shen, DIGITIMES [Tuesday 8 May 2012]

NAND flash memory is among the key components used in today's popular consumer technology products. The birth of NAND flash could be credited to two Bell Labs researchers who fabricated the world's first floating-gate nonvolatile memory (NVM) memory device. Simon Sze was one of the inventors.

Along with William Shockley's discovery of the transistor effect, and integrated circuits invented by Jack Kilby and Robert Noyce, Sze's invention with Dawon Kahng of floating-gate NVM devices was one of the major breakthroughs in semiconductor technology.
Kahng and Sze proposed the first floating gate device in 1967, around the same time when IBM invented dynamic random access memory (DRAM) cells. IBM's computer memory breakthrough drew much attention actually, Sze recalled. DRAM memory grew its adoption rapidly in PCs during the 1970s, and has become a commodity type of chip.

However, with consumer habits changing, the DRAM business is now encountering a shrinking market for traditional PCs. Sze indicated that the market for NAND flash chips had not been practically developed until the 1990s when mobile phones started to be widely used.

NAND flash is one of the NVM types, which can keep stored data when a device's power is turned off, while DRAM functions more like the "working memory" in a computer, Sze said. Both have their own expertise to satisfy different market demands.

Unlike DRAM chips that immediately replaced magnetic core chip technology as the main computer memory when first introduced, NVM memory devices were not commercialized until about 20 years after their debut, Sze observed.
Floating-gate NVM devices were introduced in 1967, and first used in end products in 1984, Sze disclosed. The memory was adopted by Nintendo in its gaming devices to automatically retain the stored information so that players can move onto the next stage, Sze said. Floating-gate devices were also first equipped into BIOS chips to speed up the boot process for PCs.
Floating-gate NVM memory started to see its wide adoption during the 1990s when demand for handsets and memory cards boomed, Sze pointed out. Memory cards using NAND flash for storing photographs began to pose a threat to the market for traditional film products, Sze added.
The popularity of Apple's i-series products does mark a turning point for NVM memory, according to Sze. The market for NAND flash memory has expanded its size big enough to challenge that of the DRAM market. According to statistics, more than 30 billion electronic products using the float-gate memory have been shipped, and the total accumulated number will top 80 billion units within the next 10 years, said Sze.
Looking forward, it is anticipated to see a new memory technology to replace floating-gate devices, Sze indicated. But the floating gate memory should maintain its presence for at least 20 years. A number of new "unified" memory devices - which come with high-speed, high-density and non-volatile features - are still in their early stages of development, Sze said.
In addition, Sze commented that the market for NAND flash will be driven by its diversified applications - from digital cameras, flash drives to smartphones, SSDs and future technology products. Demand for NAND flash will boom thanks to the memory's high density, low power, non-volatile, rewritable and small size.

Sze also suggested that the Taiwan semiconductor industry should enhance its relationship with China in order to stay competitive. The government should adopt a more open policy to attract talents and investment as the development of the island's economy and industry should not be disrupted by political issues, Sze urged.

Sze made the comments during his recent presentation at National Chiao-Tung University (NCTU), Taiwan.