Intel Fabricating 14nm ARM Chips

Consolidation of semiconductor manufacturing is pushing Altera to use Intel as its foundry. Similar to Apple using Samsung for it DRAM, NAND memory, and microprocessors (A4-A7).

"Altera announced that its Stratix 10 system-on-a-chip (SoC) will incorporate a "high-performance, quad-core 64-bit ARM Cortex-A53 processor."

That chip will be manufactured for Altera by Intel on its most advanced 14-nanometer manufacturing process. Current Intel chips on the market, such as its Haswell processor, are made on a 22-nanometer process."

More below

 

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

 

 

Irony alert: Intel to make quad-core 64-bit ARM chip

 

 

 

by Brooke Crothers

 October 29, 2013

 

 October 29, 2013

In what can only be described as highly ironic, Intel is set to make what will easily be one of the first quad-core 64-bit ARM processors.

On Tuesday, Altera announced that its Stratix 10 system-on-a-chip (SoC) will incorporate a "high-performance, quad-core 64-bit ARM Cortex-A53 processor."

That chip will be manufactured for Altera by Intel on its most advanced 14-nanometer manufacturing process. Current Intel chips on

the market, such as its Haswell processor, are made on a 22-nanometer process. Generally, the smaller the geometries, the more advanced the process.

Apple recently announced the first 64-bit chip -- also based on an ARM design -- for smartphones, the A7. But the CPU is dual-core (the graphics component is quad-core).

Intel confirmed with CNET that the chip would constitute the first 64-bit quad-core ARM CPU.

"Altera and Intel are pleased with the early results of the relationship between the companies and this announcement from Altera is consistent with the agreement we announced earlier this year. We have said that we will be open to manufacturing competitive architectures and would evaluate them on a case by case basis," said Intel spokesman Chuck Mulloy.

The quad-core 64-bit ARM chip is part of semiconductor device called a field-programmable gate array or FPGA, which is a chip that can be configured by a customer after manufacturing.

In this case, the chip is targeted at high-end networking and communication equipment, among other specialized applications, so it won't be competing directly with the likes of Samsung, Nvidia, or Qualcomm. Those companies supply processors to smartphone and tablet makers.

But it does mean that Intel is leading the charge on manufacturing multiprocessors based on designs from ARM -- a rival of Intel's in the smartphone and tablet markets.

And it does point to the potential conflicts that lurk in its contract manufacturing business, aka "foundry" business, founded in 2010 -- for which Intel is aggressively recruiting talent.

Intel is slated to begin production in 2014.

 

 

 

 

DDR4- Latest DRAM is Here

On May 2012 Micron announced DDR4 samples - First DDR4 DRAM from Micron



More about DDR4 at Why migrate to DDR4?

• "Improved capacity and performance scalability: 

DDR4 is organized differently from DDR3—specifically in the area of how DDR4 is designed to support high-speed multi-core processors. The 8-Gb DDR4 SDRAM device with 4-bit-wide data bus interface (x4), for example, is internally organized as a device with four bank groups and four banks in each bank group...

• Improved power efficiency:

Aside from further reducing the DRAM I/O voltage (VDDQ) from 1.35 V used by DDR3L DRAM devices to 1.2 V, the DDR4 SDRAM device also specifies that a separate VPP voltage supply be provided to support high DRAM core word line voltage requirements...

• Improved reliability, availability and serviceability (RAS):

 DDR4 SDRAM specification improves RAS is that DDR4 device supports command and address parity error detection, as well as recovery from parity error...supports a connectivity test mode, so that a system controller can test and detect connectivity faults without needing to go through DRAM initialization sequencing...The DDR4 register also provides enhanced RAS over the DDR3 register in that the DDR4 register can be configured to support command blocking upon detection of a parity error.."


It will still be awhile before DDR4 will replace DDR3.

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/
 

DDR4 You Can Use Now

Kristin Lewotsky

10/17/2013 10:30 AM EDT 

After seven years of development, JEDEC released the DDR4 DRAM standard (JESD79-4) last fall. The standards committee recognized the ever-increasing performance demands placed on memory and knew that a simple update wouldn't be enough.

The DDR4 architecture represents a major departure from that of previous DRAM standards, affording significant performance improvement, dramatic reductions in power demand, and compatibility with 3D architectures. Typically, a couple of years elapses between the release of a standard and broad availability of product.
Given the rapid evolution of the technology, however, DDR4 is expected to mature quite a bit more rapidly than its predecessors, with broad deployment hitting in 2014. Indeed, at the recent Intel Developers Forum (IDF), companies demonstrated working systems, like Kingston Technology's memory demo highlighting 192 GB of working 2133 MT/s DDR4 Registered DIMMs at 1.2V operating on a future Intel reference platform. We thought it was a good time to take a look at some of the offerings out on the market available to design engineers.
The following slideshow reveals that the products curently sampling go beyond memory modules to include controllers and chipsets.

SDRAM controller and PHY (Altera)SDRAM controller and PHY (Altera)

A DDR4 SDRAM interface solution provides a flexible method for designers to interface external memory with FPGAs and SoCs. The Altera PHY megafunctions and associated High-Performance Memory Controller II (HPMCII) are two distinct offerings that can be used together or individually. The PHY megafunctions provide the interface between the memory controller and the external memory devices, performing read and write operations to memory. It can be used as part of the HPMCII MegaCore function to create a complete controller and PHY solution for DDR4 SDRAM, or they can be used separately with a custom controller.

DDR4 DRAM (Micron)DDR4 DRAM (Micron)

Micron's 8 Gb DDR4 DRAM operates at data rates as high as 2400 MT/s. By leveraging the power saving options enabled by the DDR4 standard, the devices deliver a 40 percent reduction in power consumption and 20 percent reduction in voltage compared to DDR3 DRAM. The components also sport a JTAG boundary scan feature to enable early fault detection during testing. At the 2013 Consumer Electronics Show, Micron's consumer line Crucial announced availability of DDR4 DRAM modules, although they do not appear currently on the company's website.

PHY IP (Synopsys)

A set of mixed-signal PHY IP cores provides a physical interface compliant to the DDR4 spec, as well as to LPDDR3 and prior editions. The Synopsys DesignWare DDR4 multiPHY IP supports DDR4 SDRAM speeds up to 2400 Mbps. Each DDR4 multiPHY encompasses an application-specific SSTL I/O library, a single address/command macro block, multiple-byte-wide data macro blocks instantiated as required to accommodate the memory channel width, and separate PLL macrocells that directly abut the address/command macro block and data macro blocks. They target 28-nm nodes and below.

Enterprise-class RDIMM (Innodisk)Enterprise-class RDIMM (Innodisk)

Innodisk a step toward the server market with the sampling of DDR4 RDIMMs. The family includes 4 GB, 8 GB, and 16 GB devices. Memory bus speeds start at 2133 MHz. With DDR4, the maximum capacity per chip has now been doubled from 64 GB to 128 GB. The higher memory densities possible with DDR4 will save space, simplify module construction, and improve internal airflow.

LRDIMM chipset (IDT)LRDIMM chipset (IDT)

This chipset for DDR4 RDIMMs and LRDIMMs combines IDT's 4DB0124 DDR4 data buffer and its 4RCD0124 registered clock driver (RCD) to provide complete buffering of command, address, clock, and data signals across an LRDIMM. Instantiating nine data buffers across the bottom of an LRDIMM with a single RCD in the center allows up to 16 ranks of DRAM to be reduced to a single load, minimizing stub lengths and physical skew between data bits and increasing the speed and bandwidth performance of LRDIMMs in multi-slot systems. The 4DB0124 supports advanced configuration and power interface (ACPI) states, which IDT claims reduces overall system power consumption.

DDR4 registering clock driver (Montage)DDR4 registering clock driver (Montage)

A dual-mode DDR4 registering clock driver (RCD) designed for next-generation server platforms can be used independently on an RDIMM or in conjunction with nine data buffers on an LRDIMM. With a variety of power-saving modes such as S3 low power mode, CK Stop mode, etc., the M88DDR4RCD01 from Montage Technology supports 1.2V VDD operations. It features a configurable 32-bit 1:2 registering buffer for address and control signals and I2C interface support.

DDR4 DRAM (Samsung)DDR4 DRAM (Samsung)

Samsung is taking aim at the enterprise server market with volume release of this family of 4 Gb DDR4 DRAM. Fabricated using 20-nm process technology, the devices deliver 2,667 Mbps operation, a factor of 1.25 greater than the company's 20-nm-class DDR3, all-consuming 30 percent less power. Current packaging includes a 78-ball BGA.

DDR4 register (Inphi)DDR4 register (Inphi)

A 0.95 JEDEC-compliant DDR4 register targeted at enterprise and IP data center supports up to DDR4-2666 memory. Inphi demonstrated its iDDR4RCD-GS02 at the Intel Developers' Forum, running a test system at speeds up to 2400 MT/s while consuming less power than DDR3-1866 modules of the same capacity. The register allows system designers to customize performance and power profile across a wider range of operating frequencies as compared to DDR3.

Apple and Samsung NAND/ DRAM Supply

Due to consolidation of semiconductor fabs and NAND memory vendors in the last few years, Apple is tied to Samsung as one of its key DRAM and NAND memory supplier.

 iPhone 5s Teardown use "SK Hynix H2JTDG8UD3MBR 128 Gb (16 GB) NAND Flash"

However MacBook Pro 15" Retina Display Late 2013 Teardown

Samsung K4P4G324EB-FGC2 512 MB Mobile DRAM

Samsung S4LNO53X01-8030 SSD Controller

Samsung K9HFGY8S5C 32 GB NAND Flash Modules (8 chips for 256 GB total)

The volume of smart phone is much larger than that of MacBook, however, MacBook use 8 NAND chips while the cell phone uses one.


Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Facebook Propels SSD Flash Storage

Facebook continues to advance the frontier of flash NAND SSD in servers and data centers. The article bellow discusses  Flashcache and other open source projects.

"internally developed caching software, called Flashcache, to more efficiently use the thousands of solid-state drives (SSDs) that the social networking giant deploys to store frequently consulted data.

The newly released Flashcache 3.0 is able to make better decisions about what data to cache, while reducing the amount of wear and tear on expensive flash disks."

Earlier in the year Facebook asked for the cheapest and slowest flash memory

and Seven Questions for Facebook Infrastructure Guru Frank Frankovsky


Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Facebook open-source cache squeezes more from flash disks

Joab Jackson@Joab_Jackson

• Oct 9, 2013 12:50 PM

Facebook continues to push the boundaries of storage and server technology in order to more quickly serve its billion users, and the results are being offered as open-source technology that can also benefit other companies.

Recently, Facebook updated its internally developed caching software, called Flashcache, to more efficiently use the thousands of solid-state drives (SSDs) that the social networking giant deploys to store frequently consulted data.

The newly released Flashcache 3.0 is able to make better decisions about what data to cache, while reducing the amount of wear and tear on expensive flash disks.

“With these improvements, Flashcache has become a building block in the Facebook stack,” wrote Domas Mituzas, a Facebook database engineer who authored a blog post explaining the updates to the open-source software.

The work aims to improve overall Facebook performance without unduly driving up operating costs.

“While the cost per GB for flash is coming down, it’s still not where it needs to be,” Mituzas wrote. Given the premium prices commanded for SSDs, Facebook doesn’t want to wear out these disks too quickly. “SSDs have limited write cycles, so we have to make sure that we’re not writing too much.”

Other open-source projects

Flashcache is one of a number of software projects that Facebook originally developed in house that the company has also released as open source. Earlier this year, for instance, the company also released a virtual machine, called HipHop, that speeds the processing of PHP code.

The company hopes that other organizations could reuse such programs as HipHop and Flashcache and eventually contribute to their further development. Like other open-source caching software such as memcache and Redis, Flashcache can be used to speed the responsiveness of a heavily visited website or popular Web application.

Facebook originally created Flashcache to boost the responsiveness of the MySQL databases that store user data. The software can be loaded onto the Linux kernel as a module without making any changes to the kernel itself.

The idea behind Flashcache is to use SSDs to hold the material that is most requested by users. SSDs tend to be faster than traditional rotating platter hard drives, though they are also more expensive by the GB when compared to hard drives. So it would not be cost-effective for Facebook to store all of its data on SSDs, especially if the vast majority of Facebook user data is rarely consulted.

FACEBOOK

Facebook found hotspots in its cache, where frequently consulted data could cluster in small areas, causing bottlenecks.

Although designed to work with MySQL and the MySQL InnoDB database storage engine, Flashcache can be used as a general caching mechanism for Linux systems.

Flashcache can also speed times it takes to write data to disk, from the user’s perspective, by saving newly updated data on SSD first and then writing it to the hard drives later.

The updated Flashcache module improves performance in read-write distribution, cache eviction and write efficiency.

Analyzing Flashcache performance, Facebook had found that most of its caches have a small subset of data that is read much more frequently than most of the other data.

With the previous version of Flashcache, 50 percent of a cache’s contents accounted for 80 percent of disk operations. Such a concentration of frequently consulted material could cause performance bottlenecks.

To improve Flashcache’s read-write distribution, the engineers developed a number of techniques to automatically position the data so that cache reads are distributed more evenly across the SSD. Now 50 percent of the cache accounts for 50 percent of the disk operations.

To improve the process of determining which data to move off the cache, a process called cache eviction, Flashcache switched from using the FIFO (first in first out) algorithm—in which the oldest data in the cache is removed first to make room for new data—to a LRU (least recently used) algorithm, which discards the data that hasn’t been requested for the longest period of time.

Improvements were also made in write efficiency.

Previously the software would write to disk only when it had a certain amount of data that was ready to be written. This resulted in uneven performance across different caches, however. So, Facebook engineers developed an approach that would write the cached data to disk whenever a copy of that data was requested by a user, which resulted in a smoother flow of write operations.

Thanks to these improvements, the updated caching mechanism has an average hit rate—or information that is requested by users that resides in cache—of 80 percent, up from 60 percent in the previous version. This means more data is served more quickly.

Updating the software has also slashed server I/O (input/output) required to read data by 40 percent, and reduced the I/O required to write data by 75 percent. For a company that is running thousands of servers, such a reduction in traffic can help make more efficient use of servers and keep hardware costs manageable.