Wednesday, August 14, 2013

Samsung 3D Stacked NAND Flash has Engineering Samples

Yesterday Samsung announced 3D flash V-NAND at Flash Summit

A key advantage of 3D vertical scaling is that device and process development issues of silicon based technology are better understood than other future flash approaches that depends on integrating brand new materials. 

Two other strong flash vendors are also developing 3D Flash

Toshiba and Hynix

There is an interesting discussion regarding 3D flash from 2009 between Samsung and Toshiba
3D Cells Make Terabit NAND Flash Possible

Based on Samsung keynote announcement at the flash summit:

 1. Samsung is having already engineering sample now and it will be in production in 2014.

2. Unless there is some unexpected development, it sound like Samsung's 3D NAND (and similar flavors by its competitors) will be the mainstream future NAND technology.

3. A key issue which they did not explain is erase cycle. They only said that erase had to be optimized with specific circuits. 

4. Samsung has been developing it since 2003. Initially they just developed the CTF memory cell technology as a standard planar NAND (see my previous comments  and at's_32-gigabit-Gbit_40-nm_CTF-NAND_uses_high-k.htm). However, that product was not a commercial sold.

6. The first 3D test product they made was 16G in 2011, the current one is 128Gb which is built using a stack of 24 layers.

7. Samsung is building it based on a standard known 30nm silicon technology, they said it is cost competitive (or cheaper?) than planar technology. I am not sure what are their assumptions are as far as cost, but they are probably correct that it will be cheaper than competing future technologies.

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