"Intel will reveal its processing secrets including its doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in mitigation of variation, its use of two levels of air-gap-insulated interconnects at 80-and-160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics"
Also IBM will discuss at IEDM adding SOI to FinFETs, which reduce their capacitance. SOI has been used by IBM for other processes, however it complicate designing circuits on the chips.
See more about FinFETs from May 2011 at - Tutorial: Intel 22nm 3D Tri-Gate FinFETs TransistorsRon
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