The article below discusses progress in applying 3D processes in fabrication of next generation flash memory.
Some of the key challenges in developing this technology are:
"challenges on the manufacturing front. In no particular order, alternating stack deposition, metal deposition, high-aspect-ratio etch and metrology are arguably the most difficult process steps for 3D NAND. “Above all, metrology was the most underestimated and under-invested for the industry’s readiness for vertical NAND,” said Naga Chandrasekaran, vice president of process R&D at Micron Technology. “We have these vertical structures and recessed structures within these vertical spaces, but we cannot measure them today....”
My 1990 patent ( Electrical measurements of the profile of semiconductor devices during their manufacturing process ) would help resolving the vertical Metrology difficulties.
More about the processing difficulties is in Applied Materials talks about 3D NAND flash production .