Manufacturing cost of iPhone 7

IHS published a "bill of materials (BOM) for an iPhone 7 equipped with 32 gigabytes (GB) of NAND flash memory carries $219.80 in bill of materials costs". See more in the article below.

Apple A10 Fusion APL1W24 SoC + Samsung 3 GB LPDDR4 RAM (from https://www.ifixit.com/Teardown/iPhone+7+Plus+Teardown/67384)

Some of the high cost chips used in the iPhone will go down in price; for example the System-on-Chip (SOC) at a cost of $26.90 (made by TSMC) and the NAND memory chips (made by Hynix) and SDRAM (made by Samsung) at a combined cost of $16.40. The price of the iPhone 7 will not go down.

Ron

Insightful, timely, and accurate semiconductor consulting.

Semiconductor information and news at - http://www.maltiel-consulting.com/

The iPhone 7 costs Apple more than you think

LONDON--(BUSINESS WIRE)--The bill of materials (BOM) for an iPhone 7 equipped with 32 gigabytes (GB) of NAND flash memory carries $219.80 in bill of materials costs, according to a preliminary estimate from IHS Markit (Nasdaq: INFO), a world leader in critical information, analytics and solutions.

“Total BOM costs for the iPhone 7 are more in line with what we have seen in teardowns of recent flagship phones from Apple’s main competitor, Samsung, in that the costs are higher than in previous iPhone teardown analyses,” said Andrew Rassweiler, senior director of cost benchmarking services for IHS Markit. “All other things being equal, Apple still makes more margin from hardware than Samsung, but materials costs are higher than in the past.”After $5 in basic manufacturing costs are added, Apple’s total cost to manufacture the iPhone 7 rises to $224.80. The unsubsidized price for a 32GB iPhone 7 is $649. IHS Markit has not yet performed a teardown analysis on the larger iPhone 7 Plus. This preliminary estimated total is $36.89 higher than the final analysis of the iPhone 6S published by IHS in December 2015.

Apple iPhone 7 32GB (A1778)
						Cost Summary
						Direct Material Costs		$	219.80
						(Component Costs)
						Conversion Costs		$	5.00
						(Assembly / Insertion / Test Costs)
						Total Cost		$	224.80
						(Direct materials and manufacturing)
Itemized Components		Manufacturer Name		Manufacturer Part Number		Description		Total Cost
Apps Processor
System-on-Chip		TSMC (Apple)		APLW24		Apple A10, Quad-Core 64-Bit ARM Based CPU, Hexa-Core GPU, 16nm FinFET		$	26.90
Baseband / RF / PA								$	33.90
Baseband		INTEL CORP		PMB9943		Baseband Processor, Multi-Mode
RF Transceiver		INTEL CORP		PMB5750		RF Transceiver, Multi-Mode (Qty:2)
RF Front End
Antenna Switch Module		TDK CORP		D5313		Antenna Switch Module, w/ Filters
Antenna Switch Module		TDK CORP		D5325		Antenna Switch Module, w/ Filters
Envelope Tracking		QORVO INC		81003M		Envelope Tracking IC
FEM		BROADCOM LTD (AVAGO)		DFI620		FEM
FEM		SKYWORKS		SKY13702-20		FEM
FEM		SKYWORKS		SKY13703-21		FEM
PAM		BROADCOM LTD (AVAGO)		AFEM-8050		PAM
PAM		BROADCOM LTD (AVAGO)		AFEM-8060		PAM
PAM		QORVO INC		RF6110		PAM
PAM		SKYWORKS		SKY77359		PAM
Battery
		HUIZHOU DESAY				Li-Polymer, 3.8V, 1960mAh		$	2.50
BT / GNSS / WLAN								$	8.00
BT / WLAN		UNIVERSAL SCIENTIFIC INDUSTRIAL		S39S00201		BT / WLAN Module
GNSS		BROADCOM LTD		BCM47734IUBG		GNSS Receiver
Front End						BT / WLAN & GNSS Front End
Cameras								$	19.90
Front FaceTime						7MP BSI w/ Fixed Lens
Rear						12MP BSI, w/ AutoFocus, & Optical Image Stabilization
Display								$	43.00
Display / Touchscreen Module						4.7" 1334x750 LTPS IPS LCD, w/ In-Cell Touch
Electromechanicals								$	16.70
Taptic Engine						Taptic Engine
Other Electro-Mechanicals						Antennas, Connectors, Microphones, PCBs, Speakers, etc.
Glue Logic								$	1.30
		LATTICE SEMICONDUCTOR		ICE5LP4K-SWG36I		FPGA - iCE40 Ultra, 40nm
Mechanicals								$	18.20
Enclosure						Enclosure, Main, Bottom - Machined Aluminum
Other Mechanicals						Hardware, Labels, Insulators, Shielding, vents, etc.
Memory								$	16.40
NAND		SK HYNIX		H23QEG8VG2ACS-BC		32GB NAND
SDRAM		SAMSUNG SEMICONDUCTOR		K3RG1G10CM-YGCH		2GB LPDDR4 PoP
Power Management								$	7.20
PMIC - Main		DIALOG SEMICONDUCTOR		338S00225		PMIC - Main
PMIC - RF		INTEL		PMB6826		PMIC - RF
Others						Other PMICs, Transistors, Diodes, etc.
User Interface								$	14.00
Audio codec		CIRRUS LOGIC		CS42L71		Audio Codec
Audio Amplifier		CIRRUS LOGIC		338S00220		Audio Amplifier (Qty:3)
NFC		NXP		PN67V		NFC Controller
Others						Interface Ics, discretes, passives, etc.
Sensors
Barometer		BOSCH SENSORTEC GMBH				Barometric Pressure Sensor
e-compass		ALPS				Electronic Compass
Other Sensors						Accelerometer, Gyroscope, Touch ID Fingerprint sensor, ALS/Proximity sensor, etc.
Box Contents								$	11.80
Lightning Cable						USB to Lightning
Lightning to 3.5mm Audio Adapter						Audio Adapter, Lightning to 3.5mm Jack
Headset w/ Lightning Connector						Headset, Stereo, w/ Lightning Connector
Charger

Same shape. No jack.

While the overall shape and physical design of the iPhone 7 is similar to the iPhone 6S that preceded it, the new display has wider color gamut, including DCI-P3 as well as traditional sRGB, which improves the rendering of photos and videos. The device’s haptic engine, which provides the “click” feel for users, has also been improved for longer-duty cycles and better dynamic response. The home button is now static and mimics the MacBook in terms of a solid-state button design.

Apple has also eliminated the 3.5 millimeter headphone jack, allowing a larger battery and haptic motor. “Where there was an audio jack in the previous design, Apple replaced it with a symmetrical grill -- not for speakers, but for the waterproof microphone, leaving more room for the larger battery and Taptic Engine,” Rassweiler said.

Increased base-model storage

Apple has increased the iPhone 7’s storage density. For the first time, the base model starts at 32 gigabytes (GB) – which is only the second time Apple has upgraded the base storage in the iPhone. From a cost perspective, the shift from 16GB/64GB/128GB iPhones to 32GB/128GB/256GB is a big jump. “Despite significant cost erosion in NAND flash over the last year, this increase in the overall memory cost definitely puts pressure on the bill of materials costs -- and therefore margins -- from Apple’s perspective,” Rassweiler said.

Intel returns

The Intel design win, and six years of absence that Intel had from the iPhone, is important to note. Even so, Intel still shares the processor business with Qualcomm. “Whereas Apple strives to have ‘one iPhone model for all carriers and markets,’ there are a number of different hardware permutations supporting various countries and carriers,” Rassweiler said. “Apple will likely look for ways to simplify the design moving forward, which means one supplier – whether Intel or Qualcomm – will likely dominate, as part of supplier and SKU streamlining.”

According to Wayne Lam, principal analyst of smartphone electronics, IHS Markit, “Largely left behind in the 4G LTE market, Intel has finally worked itself back into the iPhone, which is a huge win, but not one that is going to be financially significant in the near term for Intel.”

RF paths

Apple has also eliminated segmented antenna bands, which means the company is pushing all radio-frequency (RF) paths to the very ends of the phone – both on the top and bottom. The aluminum uni-body construction and design forces all RF paths into those two locations. Whereas other smartphones use a glass back and RF components with antennas mounted on the ample back spaces, Apple is restricted to just two physical antennas. “This design limitation may force Apple to go back to an all-glass design again so that they can fit in 4x4MIMO LTE antennas and more features like wireless charging in the next iPhone iteration,” Lam said.

Modem moved

The baseband thin modem has been moved next to the A10 processor. Prior to the iPhone 7, the thin modem was always on the other side of the SIM card receptacle. “This is a subtle change but likely shows us where Apple wants to take this,” Lam said, “eventually putting the thin modem right on the apps processor package or even integrating it into the A-series processor.”

Officially water resistant

iPhone 7 is now officially rated as water resistant. “We also saw evidence of this water proofing design evolution in the earlier iPhone 6S, which included additional gasketing around critical connectors, as well as the use of WiFi antenna at the end of the primary speaker box,”Lam said. “Doing so pushes the antennas near the only other opening, for better reception and transmission.”

Jet-black polished case

Jet black polish is a new option on 128GB and 256GB models. “This is a new feature that produces a whole new look for the iPhone,” Lam said. “It is a lower yielding, time-intensive manufacturing step that adds cost, as well as considerable value, pushing the retail price higher for those requesting this option.”

Antenna speaker design

The antenna speaker design on the iPhone 7 came from the WiFi antenna packed into the speakers of Apple’s MacBook. “Apple likes to reuse these unique designs throughout their product lines,” Lam said. In a first for the iPhone series, the headset speaker now doubles as a stereo speaker.

Upgraded camera

While not as groundbreaking as the two optical paths in the iPhone 7 Plus, the iPhone 7 camera has now been upgraded to optical image stabilization (OIS), for better low light performance.

Improved battery life

The battery has been increased to 1960mAhr capacity from 1715mAh in the previous iPhone 6s. This change is consistent with Apple’s claims of improved battery life.

IHS Markit (www.ihsmarkit.com)

IHS Markit (Nasdaq: INFO) is a world leader in critical information, analytics and expertise to forge solutions for the major industries and markets that drive economies worldwide. The company delivers next-generation information, analytics and solutions to customers in business, finance and government, improving their operational efficiency and providing deep insights that lead to well-informed, confident decisions. IHS Markit has more than 50,000 key business and government customers, including 85 percent of the Fortune Global 500 and the world’s leading financial institutions. Headquartered in London, IHS Markit is committed to sustainable, profitable growth.

IHS Markit is a registered trademark of IHS Markit Ltd. All other company and product names may be trademarks of their respective owners © 2016 IHS Markit Ltd. All rights reserved.

Contacts

IHS Markit
Lee Graham, +1 303-397-2468

Process Challenges of 3D (Vertical Transistors)

The article below describes the drive toward 3D vertical transistors above the surface of the chip's die.

"3D NAND represents a major departure from today’s planar NAND. In 2D NAND, the fabrication process is dependent on advanced lithography. In 3D NAND, though, vendors are using trailing-edge 40nm to 20nm design rules. Lithography is still used, but it isn’t the most critical step. So for 3D NAND, the challenges shift from lithography to deposition and etch.”

However the new 3D processes are not easy to implement.

"3D NAND introduces a number of new and difficult process steps to the semiconductor industry...."it has introduced several fairly complex and new processes. Uniformity of these processes is critical. So, from my perspective, the challenges here are focused on variability control of several key processes.”

It will be interesting how well Intel and Micron XPoint (see SSD, 3D Vertical NAND, or 3D XPoint?) products will succeed against current 3D products (see November 2012 3D NAND flash is coming)

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

How To Make 3D NAND

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Foundries progress with complex combination of high-aspect ratio etch, metal deposition and string stacking.

MAY 23RD, 2016 - BY: MARK LAPEDUS

In 2013, Samsung reached a major milestone in the IC industry by shipping the world’s first 3D NAND device. Now, after some delays and uncertainty, Intel, Micron, SK Hynix and the SanDisk/Toshiba duo are finally ramping up or sampling 3D NAND.

3D NAND is the long-awaited successor to today’s planar or 2D NAND, which is used in memory cards, solid-state storage drives (SSDs), USB flash drives and other products.

There is still huge demand for today’s planar NAND, but this technology is basically reaching its physical scaling limit. Today, NAND flash vendors are shipping planar parts at the mid-1xnm node regime, which represents the end of the scaling road for the technology.

So to extend NAND, OEMs want 3D NAND. 3D NAND is shipping, but the technology isn’t expected to hit the mainstream until 2017, which is one to two years longer than expected.

3D NAND is more difficult to make than previously thought. Unlike 2D NAND, which is a planar structure, 3D NAND resembles a vertical skyscraper. A 3D NAND device consists of multiple levels or layers, which are stacked and then connected using tiny vertical channels.

Today’s leading-edge 3D NAND parts are 32- and 48-layer devices. Scaling 3D NAND to 64 layers and beyond presents some major challenges. And in fact, today’s 3D NAND is expected to hit the ceiling at or near 128 layers.

“This is the limitation,” said Er-Xuan Ping, managing director of memory and materials within the Silicon Systems Group at Applied Materials. “Up to a certain point, a single-string is limited by etching or other process steps.”

So to extend 3D NAND beyond 128 layers, the industry is quietly developing a technology called string stacking. Still in R&D, string stacking involves a process of stacking individual 3D NAND devices on top of each other. For example, if one stacks three 64-layer 3D NAND devices on top of each other, the resulting chip would represent a 192-layer product. The trick is to link the individual 64-layer devices with some type of interconnect scheme.

String stacking is already in the works. For example, Micron Technology, according to multiple sources, recently demonstrated a 64-layer 3D NAND device by stringing two 32-layer chips together.

This is not a simple technology to develop, however. And even with string stacking, 3D NAND would top out at or around 300 layers, according to experts.

All told, 3D NAND is projected to remain viable at least until 2020 and perhaps beyond. “This is a 10-plus year roadmap and we are just at the beginning of it,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research.

In any case, OEMs will need to get a handle on the 3D NAND manufacturing issues in order to have more realistic expectations about their design schedules. To help OEMs, Semiconductor Engineering has taken a look at some of the more challenging process steps for 3D NAND. This includes alternating step deposition, high aspect ratio etch, metal deposition and string stacking.

Why 3D NAND?
In today systems, the memory hierarchy is fairly straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. And disk drives and NAND-based SSDs are used for storage.

NAND, a nonvolatile memory technology, is based on the traditional floating gate transistor structure. Thanks to 193nm immersion lithography and multiple patterning, vendors have extended planar NAND down to the 1xnm node regime.

But at 1xnm, there are issues cropping up. “In fact, the floating gate is seeing an undesirable reduction in the capacitive coupling to the control gate,” said Jim Handy, an analyst with Objective Analysis.

So, today’s planar NAND will soon stop scaling, prompting the need for 3D NAND. Basically, 3D NAND resembles a vertical skyscraper or layer cake. The layers, which are horizontal, are the active wordlines. “The bitlines also run horizontally in the metal layers on the top of the chip,” Handy said. “The vertical channels are the NAND ‘strings’ that attach to the bitlines.”

Meanwhile, vendors are at various stages of ramping up the technology. Samsung, the leader in 3D NAND, last year shipped its third-generation 3D NAND device—a 48-layer chip. In addition, Micron and its 3D NAND partner, Intel, have recently begun shipping their first 3D NAND chip—a 32-layer device. Both SK Hynix and the SanDisk/Toshiba duo are separately sampling 48-layer chips.

2016 is expected to be a big year for 3D NAND. At the end of 2015, there was a total of 160,000 wafer starts per month (wspm) in terms of worldwide installed capacity for 3D NAND, according to Lam Research. “We estimate that the industry will ship approximately 350,000 to 400,000 wspm of 3D NAND capable capacity by the end of 2016,” Lam’s Pan said.

Still, 3D NAND represents a fraction of the total installed capacity for NAND (2D and 3D), which is roughly 1.3 million to 1.4 million wspm. “Eventually, we expect a significant majority of the NAND installed base to become 3D capable,” Pan said.

Vendors are ramping up these devices in new or converted 3D NAND fabs. In total, the equipment cost for a 2D NAND fab ranges from $30 million to $45 million for 1,000 wspm, according to Christian Dieseldorff, an analyst with the Industry Research & Statistics group at SEMI.

In comparison, the equipment cost for a 3D NAND fab ranges from $50 million to $65 million for 1,000 wspm, Dieseldorff said. “3D NAND equipment costs are higher because more equipment like CVD and etch tools are needed,” he said.

Some vendors are retrofitting their current fabs into 3D NAND facilities. “We expect 2X to 4X more space is needed when converting from 2D to 3D. In this case, there is a high degree of re-use because most equipment is already there. Again, additional CVD and etch tools are needed,” he said.

Still, a 3D NAND fab is not as expensive as a leading-edge logic fab. A 7nm logic processes, for example, will require a $160 million fab equipment investment for every 1,000 wspm, according to Gartner.

The new litho: alternating stack deposition 
In any case, 3D NAND represents a major departure from today’s planar NAND. In 2D NAND, the fabrication process is dependent on advanced lithography. In 3D NAND, though, vendors are using trailing-edge 40nm to 20nm design rules. Lithography is still used, but it isn’t the most critical step. So for 3D NAND, the challenges shift from lithography to deposition and etch.

In fact, 3D NAND introduces a number of new and difficult process steps to the semiconductor industry. “By moving the bit-string into the third-dimension, this technology eases many of the patterning-scaling challenges,” said David Fried, chief technology officer at Coventor. “But it has introduced several fairly complex and new processes. Uniformity of these processes is critical. So, from my perspective, the challenges here are focused on variability control of several key processes.”

The 3D NAND flow starts with a substrate. Then, vendors undergo the first major challenge in the flow—alternating stack deposition. Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer on the substrate.

This process is much like making a layer cake. In simple terms, a layer of material is deposited on the substrate. Then, another layer of material is deposited on top of that. The process is repeated several times until a given device has the desired number of layers.

Each vendor uses a different set of materials to create a stack of layers. For example, to make its 3D NAND devices, Samsung deposits alternating layers of silicon nitride and silicon dioxide on the substrate, according to Objective Analysis. In contrast, Toshiba’s 3D NAND technology consists of alternating layers of conductive polysilicon and insulating silicon dioxide, according to the firm.

Alternating stack deposition must have precise control with good uniformities and low defectivity. “Initially, the uniformities must be good,” Applied’s Ping said. “It’s all going back to stress control because the alternating films are different. For each film there could be a mismatch. Stress could show up.”

The challenges escalate as vendors increase the number of layers in a device. “Repeatability at every single step is also critical and it has to be done at high productivity in order to keep costs down,” Lam’s Pan said.

High aspect ratio etch
Following the alternating stack deposition step, a hard mask is applied on the surface and holes are patterned on the top. Then, here comes the hardest part of the flow—high-aspect ratio etch.

Tiny trenches or channels are etched from the top of the device to the substrate. To illustrate the complexity of this step, Samsung’s 3D NAND device has 2.5 million tiny channels in the same chip. Each of them must be parallel and uniform.

Today’s high-aspect ratio etch tools can handle the requirements for 32- and 48-layer devices. For these chips, the aspect ratios range from 30:1 to 40:1. “This etch is really complex. Uniformity is absolutely critical to the performance of the memory device,” Coventor’s Fried said. “The statistics are also staggering. Once the etch is complete, the amount of processing that takes place inside that hole is also pretty impressive.”

The problem? Current high aspect ratio etch tools are either not ready or struggling to meet the demands for 64-layer devices and beyond. At 64 layers, the aspect ratios are 60:1 to 70:1. “This is too high for current etching capability,” Applied’s Ping said. “The etching and hard mask technologies are not necessarily available for 60:1 or 70:1.”

So going forward, NAND vendors are simultaneously following two paths. First, they will wait for the next-generation high-aspect ratio etch tools and other technologies to arrive. And then, provided the etchers are ready on time, they may scale today’s 3D NAND in the following progressions—32 and 48 layers, to 64 layers, to 96, and then to 128.

In the second path, NAND vendors also will develop next-generation string stacking technology (see below for details).

Charge trap versus floating gate 
Before moving to string stacking, vendors will continue to scale today’s 3D NAND. Besides deposition and etch, today’s 3D NAND undergoes other complex steps, including the formation of the gate.

For this, the industry is moving in two directions. Samsung, SK Hynix and the SanDisk/Toshiba duo are making use of charge trap flash technology. This technology uses a non-conductive layer of silicon nitride. The layer wraps around the control gate of a cell, which, in turn, traps electrical charges to maintain cell integrity.

In contrast, the Intel/Micron duo are not using charge trap. Instead, they have extended the floating gate structure to 3D NAND. “In floating gate, the gate is actually a conductor,” Objective Analysis’ Handy said. “A charge trap layer, which actually looks like a floating gate, is an insulator.”

Floating gate involves some difficult patterning steps. “It’s hard to pattern things on the sides of a vertical hole that you’ve made. You have to go through a lot of process steps,” Handy said.

Charge trap also has some drawbacks. “The advantage with charge trap is that you don’t have to pattern it. Charge trap is easier to make that way,” he said. “Excluding Spansion, which ships over 80% of all bytes in charge trap, nobody else has been able to make charge trap cost effectively.”

Metal deposition
Once the gate is developed, the next step is difficult. The device requires contacts. The device is backfilled with a conductor using a metal deposition step.

“There is a challenge in the metal deposition area,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “We’re seeing a lot of customers’ backfilling it with tungsten. And that’s a tricky deposition, because you are doing a non-line-of-sight deposition. So you basically have these caves and tunnels in there. You have to go back in there after the fact and put in tungsten metal. If you don’t engineer the process right, you may put in this pre-cursor that wants to plate out metallic tungsten. Given its own way, it could plate out right when it gets into the hole. So you have a lot of ways to create voids.”

String stacking
There are other difficult steps in the flow, but the biggest challenge is clear. Until the industry solves the high aspect ratio etch issues, today’s single-string 3D NAND technology is arguably stuck at 48 and/or 64 layers.

And even when the etchers are ready, today’s single-string 3D NAND hits the wall at 128 layers. “This is because the aspect ratio is limited by the process,” Applied’s Ping said. “So you must figure out a way to bypass the limitations.”

So what’s the answer? String stacking. In this approach, vendors will stack individual 3D NAND devices. Each device might be separated by an insulating layer. “When you do string stacking, you finish one string,” Ping said. “Then, you are repeating the steps. It’s difficult, but you can do it.”

For example, a vendor will develop a 48-layer device. To devise that chip, it will go through the same process flow, such as alternating layer deposition, etch and others.

Then, the vendor will develop a separate 48-layer chip using the same flow. The process is not limited to 48-layer chips. A vendor could also stack multiple 32-layer chips. And if the technology is available, a vendor could stack 64-, 96- and perhaps 128-layer devices.

In theory, though, vendors may opt for string stacking with 32- and 48-layer chips. There is less stress for an individual 32- or 48-layer device, as compared to a 96- or 128-layer chip.

Ultimately, though, 3D NAND with string stacking may run out of steam at or near 300 layers. “It will hit a problem in terms of yield,” Ping said. “When you stack, the yield loss from defects continues building up. That will be the limitation. Plus, everything will be limited by stress. If you put too much film, then the stress presents a limitation.”

Still to be seen, however, is how vendors will connect the individual 3D NAND devices together in string stack. For this, the industry is looking at various interconnect schemes. “There will be four or five different options,” he said. “You can build a shared bit line in the middle. Then, another option is that you build a string, which contacts each string directly.”

To be sure, though, there are still many unknowns and challenges with string stacking. The industry also faces several challenges even without string stacking. In either case, the industry must continue to master and perfect the various process steps with 3D NAND. Otherwise, the technology will remain costly, at least for the vast majority of OEMs.

Semiconductor Foundries Grew 4.4% while Global Sales Fell 2% in 2015

"The global semiconductor foundry market grew 4.4 percent in 2015 to reach $48.8 billion in value, according to market research company Gartner" (more below).

Semiconductor foundries were able to still grow their business in 2015 even though the overall demand for semiconductors shrunk. Of the foundries based in China, the largest foundry- SMIC had the largest increase in growth of 13.1%.

At the same time, the overall semiconductor market shrunk more than 2% in 2015 - See tables below.

Global Semiconductor Market Slumps in 2015, IHS Says

Worldwide Semiconductor Revenue Declined 2.3 Percent in 2015, According to Final Results by Gartner)

Ron

Insightful, timely, and accurate semiconductor consulting.

Semiconductor information and news at - http://www.maltiel-consulting.com/

FOUNDRY MARKET STALLS, FUJITSU CLIMBS RANKING

The global semiconductor foundry market grew 4.4 percent in 2015 to reach $48.8 billion in value, according to market research company Gartner Inc.

The percentage increase was low, coming after three years of double-digit percentage growth, but still was greater than the overall chip market which contracted by 2.3 percent in 2015, according to Gartner (see Chip market fell 2.3% in 2015, says Gartner ).

TSMC was market leader and is it has been for many years, and grew by 5.5 percent in 2015 driven by the success of its 20nm planar CMOS and 16nm FinFET manufacturing processes serving the needs of application processors and baseband modem chips.

Globalfoundries was able to outgrow UMC and swapped places with the Taiwanese foundry in second position, mainly due to the contribution of its IBM acqusitions. Samsung and SMIC grew faster than both of these companies but were unable to improve their rankings.

Top 10 semiconductor foundries ranked by 2015 revenue in $millions. Source: Gartner.

Tower Semiconductor Ltd., which trades as TowerJazz, grew strongly in 2015 but remained in 7th spot. Fujitsu which was 10th in 2014 climbed to position 8 in 2015 while Vanguard and Hua  Semiconductor both dropped a single ranking position.

Price competition in advanced process technologies in 2015 was exceptionally strong, not only on the 28 nm node, as more foundry suppliers have started the production volume of 28 nm polySiON technology, but also on 65 nm and 40 nm. In contrast to the highly utilized 200 mm fabs from fingerprint ID chips and power management ICs, the low 300 mm fab utilization rates at some large foundries have triggered their willingness to run more 0.18-micron wafers in the 300 mm fabs.

Semiconductor Revenue Growth, Ranking

Worldwide semiconductor revenue declined 1.9% in 2015 (see article below) while fab capacity increased 6% .  Samsung and Hynix benefited from the iPhone 6s demand. 

The ranking will change in 2016 due to recent trouble of Toshiba and Western Digital buying SanDisk . As in past ranking SanDisk revenue is not included, which make this table inaccurate (see April 2012 blog Top 25 2011 Semiconductor Sales Ranking )

Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/

Gartner Says Worldwide Semiconductor Revenue Declined 1.9 Percent in 2015

Mixed Results in All Segments Drove Slow Growth

Worldwide semiconductor revenue totaled $333.7 billion in 2015, a 1.9 percent decrease from 2014 revenue of $340.3 billion, according to preliminary results by Gartner, Inc. The top 25 semiconductor vendors' combined revenue increased 0.2 percent, which was more than the overall industry's growth. The top 25 vendors accounted for 73.2 percent of total market revenue, up from 71.7 percent in 2014.

"Weakened demand for key electronic equipment, the continuing impact of the strong dollar in some regions and elevated inventory are to blame for the decline in the market in 2015," said Sergis Mushell, research director at Gartner. "In contrast to 2014, which saw revenue growth in all key device categories, 2015 saw mixed performance with optoelectronics, nonoptical sensors, analog and ASIC all reporting revenue growth while the rest of the market saw declines. Strongest growth was from the ASIC segment with growth of 2.4 percent due to demand from Apple, followed by analog and nonoptical sensors with 1.9 percent and 1.6 percent growth, respectively. Memory, the most volatile segment of the semiconductor industry, saw revenue decline by 0.6 percent, with DRAM experiencing negative growth and NAND flash experiencing growth."

Intel recorded a 1.2 percent revenue decline, due to falls in PC shipments (see Table 1). However, it retained the No. 1 market share position for the 24th year in a row with 15.5 percent market share. Samsung's memory business helped drive growth of 11.8 percent in 2015, and the company maintained the No. 2 spot with 11.6 percent market share.

Rank 2014	Rank 2015	Vendor	2014 Revenue	2015 Estimated Revenue	2014-2015 Growth (%)	2015 Market Share (%)
1	1	Intel	52,331	51,709	-1.2	15.5
2	2	Samsung Electronics	34,742	38,855	11.8	11.6
5	3	SK Hynix	15,997	16,494	3.1	4.9
3	4	Qualcomm	19,291	15,936	-17.4	4.8
4	5	Micron Technology	16,278	14,448	-11.2	4.3
6	6	Texas Instruments	11,538	11,533	0.0	3.5
7	7	Toshiba	10,665	9,622	-9.8	2.9
8	8	Broadcom	8,428	8,419	-0.1	2.5
9	9	STMicroelectronics	7,376	6,890	-6.6	2.1
12	10	Infineon Technologies	5,693	6,630	16.5	2.0
		Others	157,992	153,182	-3.0	41.2
		Total	340,331	333,718	-1.9	100

"The rise of the U.S. dollar against a number of different currencies significantly impacted the total semiconductor market in 2015," said Mr. Mushell. "End equipment demand was weakened in regions where the local currency depreciated against the dollar. For example in the eurozone, the sales prices of mobile phones or PCs increased in local currency, as many of the components are priced in U.S. dollars. This resulted in buyers either delaying purchases or buying cheaper substitute products, resulting in lower semiconductor sales. Additionally, Gartner's semiconductor revenue statistics are based on U.S. dollars; thus, sharp depreciation of the Japanese yen shrinks the revenue and the market share of the Japanese semiconductor vendors when measured in U.S. dollars."

The NAND market continued to deteriorate throughout the year. As a result, revenue grew only 4.1 percent in 2015, fueled by elevated supply bit growth that resulted in an aggressive pricing environment. The tumultuous NAND pricing environment rippled through most of the NAND solutions, particularly solid-state drives (SSDs), which continue to encroach on hard-disk drives (HDDs). The ensuing price war in SSDs further pressured the profitability of the NAND flash makers amid the biggest technology transition in flash history — 3D NAND. While 3D NAND commercialization was modest, it was limited to only one vendor — Samsung. Modest revenue gains have not stopped investment in NAND flash and 3D technology, with all vendors continuing to spend aggressively in the technology and most with new fabs.

After 32.0 percent revenue growth in 2014, the DRAM market hit a downturn in 2015. An oversupply in the commodity portion of the market caused by weak PC demand led to severe declines in average selling prices (ASPs), and revenue contracted by 2.4 percent compared with 2014. The oversupply and the extent of ASP declines could have been significantly worse if Micron Technologies' bit growth had performed in line with its South Korean rivals. Fortunately for the market, the company saw negative bit growth due to its transition to 20 nm, sparing the industry from an even more severe downturn.

Additional information is provided in the Gartner report "Market Share Analysis: Semiconductors, Worldwide, Preliminary 2015 Estimates."