Speed, band width and low power continue to be key goals for
semiconductor DRAM memories. The article below discusses DDR4, LPDDR4, and
GDDR5, DIMMS, and JEDEC standards.
Some of the same issues are also key
concerns for NAND flash memories. However, 3D NAND fabrication processes are
closer to production.
Ron
Insightful, timely, and accurate semiconductor consulting.
Semiconductor information and news at - http://www.maltiel-consulting.com/
Janine Love
1/7/2015 11:00 AM EST
As 2014 was winding down, there was still a lot of talk about 3D memory, mobile memory, high-performance memory, and "next-gen" memory. So what trends and challenges will make the most noise in 2015? EE Times recently spoke with Jennie Grosslight, the memory test product manager at Keysight Technologies, about what she thinks will be the prevailing memory trends in 2015.
As the memory test product manager, Grosslight is responsible for Keysight's logic analysis and compliance test tools for memory applications. With 25 years of experience and an electrical engineering degree from the University of Colorado, she has worked as an R&D engineer, technical marketing engineer, and product marketing engineer. She has been focused on helping engineers analyze and validate memory systems for the past 11 years.
What can we expect for memory in 2015? What are the trends you see?
Price, power, and performance will continue to be the driving features of memory deployment. Both DDR4 and LPDDR4 offer impressive performance improvements and power savings. DDR4 will see broader deployment to replace DDR3 in servers and begin "trickle-down" deployment in high-end desktop workstations. This will improve cloud performance and save power. LPDDR4-based products will hit the market, and mobile memory will take over as the technology driver for the memory industry overall. As DDR4 and LPDDR4 DRAM sales increase, prices will decrease, driving even more design starts with these technologies. Finally, universal flash storage-based products will be formally introduced, laying the foundation for a quantum jump in mobile systems performance and price/performance.
If you could tell engineers one thing about memory test, what would it be?
DDR memory is at the heart of today's cloud computing servers -- most of them having at least 24 DIMMs across four channels. With some data centers reporting that DDR memory is the second-highest failure they experience, the need for robust testing of designs continues to grow. To increase margin and overall performance and create a reliable and robust system, close attention to physical layer and functional testing, characterization, and debug to validate that the system is operating within JEDEC specifications is a critical step.
What has surprised you most about memory development over the past 3-5 years?
In the industry, the biggest surprise has been the emergence of the "Memory Wall" as a fundamental issue, its impact on computing architectures, and the incredible burst of innovation it has stimulated. For the past 10 years, memory has progressed along an evolutionary path, with DDR succeeding SDR, then DDR2, DDR3, and DDR4. Now, everything from 3D silicon cubes to distributed memory architectures and completely new signaling methods are in development with some already deployed. Every few months a new possibility seems to emerge for consideration. It's the most interesting time to be involved in memory in the last 20 years. Along this evolutionary path, lower power and increased data rates in LPDDR technologies for mobile applications continues to push the limits. The LPDDR specification in mobile applications now has the performance of DDR technologies in computing.
From a memory test perspective, it is surprising to see that there are servers being shipped without testing to specifications. Simply designing to recommended guidelines and running software tests to validate system operation doesn't validate that the system is operating within specifications. When systems violate functional or parametric specifications for DDR/LPDDR memory, the system may not fail with each violation. However, as the number of violations increase, so does the rate of memory failures. The degree of difficulty in testing different DDR or LPDDR memory is highly dependent on the layout of the system under test and associated subsystem verification. To ensure this verification has occurred, data centers should consider requiring qualification reports.
What are the major stoppers/technical hurdles for mobile memory? Storage?
Reducing power consumption, total memory channel throughput, and signal density are the key requirements and hurdles. Interfaces need to get faster, wider, denser, or some combination of these to improve channel throughput. Packages need to pack more signals, and this increased signal density causes cross-talk effects. Traditional single-ended signaling beyond 3Gbit/s is very hard and power hungry. Very wide I/O using 3D silicon stacking is still exotic and expensive. Combining these multiplies the difficulties. A lot of experimentation, analysis, and advancements will be required to figure out the best way to overcome these challenges. Both DDR4 and LPDDR4 specifications include multiple enhancements in these areas.
Editor's Note: DesignCon 2015 takes on these topics. If you have an interest in this, see Track #7: Design Parallel and Memory Interfaces.
Are standards keeping up? Do we need more/fewer?
The standards are keeping up for the most part. The main decision is what to standardize. Until now, the memory standards have been defined by the main application: desktop/server, graphics, mobile, and mass storage. The latest generations have borrowed heavily from each other to get the best performance. DDR4 has many features first done in GDDR5. LPDDR4 looks more like its desktop cousin, DDR4, than any previous generation. Going forward, standards may be classified more by the core technology, signaling system, and interconnect method than the traditional scheme. At some point, the parallel interface with DDR memory may not be able to keep up with the faster data rate. Serial lane interfaces could be considered to address that. Continued leadership and participation with JEDEC in writing and reviewing the memory standards by companies such as Keysight and their partners, such as FuturePlus Systems, will be a key part in ensuring the necessary test specifications are being created.
How does testing differ for the various memory types? Are some memory types easier to test than others? Why?
First, read and write data separation is a very challenging task in a memory designer's work. At lower speeds, the phase difference between DQS and DQ is very obvious. Read is edge aligned with data, and write is centered aligned with data. At higher speeds, especially with LPDDR4, the phase difference between the read and write cycle is not obvious, and the preamble patterns are similar. Separating read and write cycles at higher speeds is more difficult. The use of different tools helps resolve this. For example, you can use a mixed-signal oscilloscope to trigger on the command using the command truth table.
Second, probing continues to become more and more difficult in memory test. For functional testing, using a DIMM or SODIMM interposer provides the fastest and easiest access. Access for chip down or PoP [package-on-package] designs requires BGA rework or designing probing into the system. For physical layer testing, since JEDEC standards are defined at the balls of the DRAM, the size and location of the DRAM dictate the difficulty of probing access.
How will memory test have to evolve to satisfy emerging trends?
Memory test is constantly evolving. Physical layer and functional layer testing must continue to keep up with the JEDEC standards and data rates. Creation of standards and test specifications, along with the early design of hardware and software test solutions to support them prior to new memory technologies being introduced into end products, will continue to be a priority, so customers always have the latest equipment for memory testing.
One example is the U4154A/B. When it is combined with the FS2510 DDR4 DIMM interposer with FS1070 conversion from our channel partner FuturePlus Systems, we can capture the entire DDR4 bus; run functional compliance testing; follow the signal flow of address, command, and data; and view bus-level signal integrity with 5ps x 5mv resolution.
Another test evolution is protocol analyzers. Protocol analyzers, such as the FuturePlus Systems DDR Detective, are targeted to look at only the address and command signals for functional memory specification parameters, power management and performance metrics, and give engineers real insight into these complicated protocols.
For physical layer and parametric testing, the mixed-signal oscilloscope is used to decode command protocols for reliable read and write data testing. The test can be done automatically with DDR compliance test software and debug tools.
What challenges will designers have to overcome in order to achieve success?
As chipsets scale to smaller processes, designers will have to move from DDR or DDR2 to DDR3, 50MHz flash to 200MHz flash, and LPDDR2 to LPDDR3. The low-speed design capacitance and fanout concepts that have worked for years in flash memory will need to be updated to high-speed digital flows based on transmission lines and precise timing. Host testing may begin to be incorporated. Memory tests have always been device and not host (memory controller) focused. Host and channel specifications would be equally important and the need to characterize both would become necessary.
Probing has always been a challenge and will continue to be. We are meeting that challenge with our new DDR4 BGA interposers like the W4633A DDR4 x4/x8 probing solution. DDR4 BGA interposer products are reliable and give a connection to the address/command/control and the DQ data signals to the U4154B. Similar new BGA and PoP probing technology that is proven to achieve data rates of 3.2Gbs is available for LPDDR4.
Finally, if the interface eventually moves to serial to enable continued increases in speed, there are existing serial standards that can be adopted. High-speed designers will have to learn serial speed concepts like bit error rates, eye masks, and dual dirac jitter/noise modeling. Test equipment that has been relied on for years will have to be upgraded and new measurement techniques applied. The concepts and products to support this are proven but will need to be mastered by a whole new group of designers.
As the memory test product manager, Grosslight is responsible for Keysight's logic analysis and compliance test tools for memory applications. With 25 years of experience and an electrical engineering degree from the University of Colorado, she has worked as an R&D engineer, technical marketing engineer, and product marketing engineer. She has been focused on helping engineers analyze and validate memory systems for the past 11 years.
What can we expect for memory in 2015? What are the trends you see?
Price, power, and performance will continue to be the driving features of memory deployment. Both DDR4 and LPDDR4 offer impressive performance improvements and power savings. DDR4 will see broader deployment to replace DDR3 in servers and begin "trickle-down" deployment in high-end desktop workstations. This will improve cloud performance and save power. LPDDR4-based products will hit the market, and mobile memory will take over as the technology driver for the memory industry overall. As DDR4 and LPDDR4 DRAM sales increase, prices will decrease, driving even more design starts with these technologies. Finally, universal flash storage-based products will be formally introduced, laying the foundation for a quantum jump in mobile systems performance and price/performance.
If you could tell engineers one thing about memory test, what would it be?
DDR memory is at the heart of today's cloud computing servers -- most of them having at least 24 DIMMs across four channels. With some data centers reporting that DDR memory is the second-highest failure they experience, the need for robust testing of designs continues to grow. To increase margin and overall performance and create a reliable and robust system, close attention to physical layer and functional testing, characterization, and debug to validate that the system is operating within JEDEC specifications is a critical step.
What has surprised you most about memory development over the past 3-5 years?
In the industry, the biggest surprise has been the emergence of the "Memory Wall" as a fundamental issue, its impact on computing architectures, and the incredible burst of innovation it has stimulated. For the past 10 years, memory has progressed along an evolutionary path, with DDR succeeding SDR, then DDR2, DDR3, and DDR4. Now, everything from 3D silicon cubes to distributed memory architectures and completely new signaling methods are in development with some already deployed. Every few months a new possibility seems to emerge for consideration. It's the most interesting time to be involved in memory in the last 20 years. Along this evolutionary path, lower power and increased data rates in LPDDR technologies for mobile applications continues to push the limits. The LPDDR specification in mobile applications now has the performance of DDR technologies in computing.
From a memory test perspective, it is surprising to see that there are servers being shipped without testing to specifications. Simply designing to recommended guidelines and running software tests to validate system operation doesn't validate that the system is operating within specifications. When systems violate functional or parametric specifications for DDR/LPDDR memory, the system may not fail with each violation. However, as the number of violations increase, so does the rate of memory failures. The degree of difficulty in testing different DDR or LPDDR memory is highly dependent on the layout of the system under test and associated subsystem verification. To ensure this verification has occurred, data centers should consider requiring qualification reports.
What are the major stoppers/technical hurdles for mobile memory? Storage?
Reducing power consumption, total memory channel throughput, and signal density are the key requirements and hurdles. Interfaces need to get faster, wider, denser, or some combination of these to improve channel throughput. Packages need to pack more signals, and this increased signal density causes cross-talk effects. Traditional single-ended signaling beyond 3Gbit/s is very hard and power hungry. Very wide I/O using 3D silicon stacking is still exotic and expensive. Combining these multiplies the difficulties. A lot of experimentation, analysis, and advancements will be required to figure out the best way to overcome these challenges. Both DDR4 and LPDDR4 specifications include multiple enhancements in these areas.
Editor's Note: DesignCon 2015 takes on these topics. If you have an interest in this, see Track #7: Design Parallel and Memory Interfaces.
Are standards keeping up? Do we need more/fewer?
The standards are keeping up for the most part. The main decision is what to standardize. Until now, the memory standards have been defined by the main application: desktop/server, graphics, mobile, and mass storage. The latest generations have borrowed heavily from each other to get the best performance. DDR4 has many features first done in GDDR5. LPDDR4 looks more like its desktop cousin, DDR4, than any previous generation. Going forward, standards may be classified more by the core technology, signaling system, and interconnect method than the traditional scheme. At some point, the parallel interface with DDR memory may not be able to keep up with the faster data rate. Serial lane interfaces could be considered to address that. Continued leadership and participation with JEDEC in writing and reviewing the memory standards by companies such as Keysight and their partners, such as FuturePlus Systems, will be a key part in ensuring the necessary test specifications are being created.
How does testing differ for the various memory types? Are some memory types easier to test than others? Why?
First, read and write data separation is a very challenging task in a memory designer's work. At lower speeds, the phase difference between DQS and DQ is very obvious. Read is edge aligned with data, and write is centered aligned with data. At higher speeds, especially with LPDDR4, the phase difference between the read and write cycle is not obvious, and the preamble patterns are similar. Separating read and write cycles at higher speeds is more difficult. The use of different tools helps resolve this. For example, you can use a mixed-signal oscilloscope to trigger on the command using the command truth table.
Second, probing continues to become more and more difficult in memory test. For functional testing, using a DIMM or SODIMM interposer provides the fastest and easiest access. Access for chip down or PoP [package-on-package] designs requires BGA rework or designing probing into the system. For physical layer testing, since JEDEC standards are defined at the balls of the DRAM, the size and location of the DRAM dictate the difficulty of probing access.
How will memory test have to evolve to satisfy emerging trends?
Memory test is constantly evolving. Physical layer and functional layer testing must continue to keep up with the JEDEC standards and data rates. Creation of standards and test specifications, along with the early design of hardware and software test solutions to support them prior to new memory technologies being introduced into end products, will continue to be a priority, so customers always have the latest equipment for memory testing.
One example is the U4154A/B. When it is combined with the FS2510 DDR4 DIMM interposer with FS1070 conversion from our channel partner FuturePlus Systems, we can capture the entire DDR4 bus; run functional compliance testing; follow the signal flow of address, command, and data; and view bus-level signal integrity with 5ps x 5mv resolution.
Another test evolution is protocol analyzers. Protocol analyzers, such as the FuturePlus Systems DDR Detective, are targeted to look at only the address and command signals for functional memory specification parameters, power management and performance metrics, and give engineers real insight into these complicated protocols.
For physical layer and parametric testing, the mixed-signal oscilloscope is used to decode command protocols for reliable read and write data testing. The test can be done automatically with DDR compliance test software and debug tools.
What challenges will designers have to overcome in order to achieve success?
As chipsets scale to smaller processes, designers will have to move from DDR or DDR2 to DDR3, 50MHz flash to 200MHz flash, and LPDDR2 to LPDDR3. The low-speed design capacitance and fanout concepts that have worked for years in flash memory will need to be updated to high-speed digital flows based on transmission lines and precise timing. Host testing may begin to be incorporated. Memory tests have always been device and not host (memory controller) focused. Host and channel specifications would be equally important and the need to characterize both would become necessary.
Probing has always been a challenge and will continue to be. We are meeting that challenge with our new DDR4 BGA interposers like the W4633A DDR4 x4/x8 probing solution. DDR4 BGA interposer products are reliable and give a connection to the address/command/control and the DQ data signals to the U4154B. Similar new BGA and PoP probing technology that is proven to achieve data rates of 3.2Gbs is available for LPDDR4.
Finally, if the interface eventually moves to serial to enable continued increases in speed, there are existing serial standards that can be adopted. High-speed designers will have to learn serial speed concepts like bit error rates, eye masks, and dual dirac jitter/noise modeling. Test equipment that has been relied on for years will have to be upgraded and new measurement techniques applied. The concepts and products to support this are proven but will need to be mastered by a whole new group of designers.
