16nm Split Gate NV (Non Volatile) Memory Cell Advance

Split gate nonvolatile memory is often used in embedded flash IC chips. An advance in nonvolatile split gate memory technology by CEA-Leti is discussed below. 

By using a self-aligned of the transistor gate above the nitride charge trapping layer, the number of masks required to make the memory cell is reduced, and the bias and size of the critical mask is also reduced. The new smaller embedded memory cell is smaller and more efficient.

"this self-aligned technology concern the precise control of the spacer memory gate shape and of the memory gate length. Spacer gate has to fulfill two difficult requirements: being as flat as possible in order to get a silicidation surface as large as possible while insuring a functional contact, and getting a steep edge in order to control the drain-junction doping."

A key issue is how manufacturable would be this new masking  process integration. For example controlling the properties of the charge trapping layer in large volume manufacturing could be difficult.

Ron

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CEA-Leti builds 16nm self-aligned split-gate memory

Posted: 17 Mar 2014  

Keywords:CEA-Leti  split-gate memories  transistor  poly-Si spacer 

CEA-Leti has developed what it says are ultra-scaled split-gate memories with a gate length of 16nm. According to the research centre, the memories demonstrate good writing and erasing performances with memory windows greater than 6V.

Split-gate flash memories are made of two transistors: an access transistor and a memory transistor with a charge-trapping layer (nitride, Si nanocrystals etc.). Split-gate architectures use a low-access voltage and minimize drain current during programming, which leads to a decrease of the programming power compared to standard one-transistor NOR memories, stated the research centre. Because programming energy decreases when memory gate length decreases, ultra-scaling is particularly relevant for contactless applications.

The memory gate has been reduced down to 16nm thanks to a poly-Si spacer formed on the sidewall of the select transistor. This approach avoids costly lithography steps during fabrication and solves misalignment issues, which are responsible for a strong variation of the electrical performances, such as the memory window.

The main challenges of this self-aligned technology concern the precise control of the spacer memory gate shape and of the memory gate length. Spacer gate has to fulfil two difficult requirements: being as flat as possible in order to get a silicidation surface as large as possible while insuring a functional contact, and getting a steep edge in order to control the drain-junction doping.

TEM images of ultra-scaled self-aligned split-gate device, with a memory 

gate length of 16nm.