Below is another example of the end of Moore's law.
See also
earlier post.
Ron Maltiel
Feature dimension reduction slowdown
http://www.eetimes.com/discussion/other/4238315/Feature-dimension-reduction-slowdown
Handel Jones , 3/20/2012 12:32 AM EDT
The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase. The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase.
1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.
2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.
3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.
Figure 1- Cost per gate.
With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.
4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.
EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.
New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.
What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.
After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.
The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.
Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.
Solid State Technology published three articles summarizing ISSCC 2013 technology trends. They "see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash... However, due to the major scaling challenges...continued increase in the use of smart algorithms and error-correction techniques...we see logic processes adopting FinFET devices.
